[PATCH] D26398: [mips][msa] Implement f16 support

[Simon Dardis via llvm-commits]

sdardis added inline comments.


================
Comment at: lib/Target/Mips/MipsSEISelLowering.cpp:3448
+
+  const bool IsN64 = Subtarget.isABI_N64();
+  const TargetRegisterClass *RC =
----------------
sdardis wrote:
> zoran.jovanovic wrote:
> > Nit: I do believe that Mips::GPR64RegClass and 64-bit variants of instructions should be used with N32 too.
> > Same is for code in MipsSETargetLowering::emitLD_F16_PSEUDO.
> Looking at this, I have found test cases where N32 requires either GPR32RegClass or GPR64RegClass depending on the context. I'll post a revised version of this patch soon. I've also found 1 or 2 places where the wrong MSA regclass is used.
I've updated this use the register class of the operand if it's a register, otherwise use GPR64 if it's not O32. Likewise for LD_F16.


================
Comment at: test/CodeGen/Mips/msa/f16-llvm-ir.ll:24-62
+ at k = external global float
+
+declare float @k2(half *)
+
+define void @f3(i16 %b) {
+entry:
+; ALL-LABEL: f3:
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New test coverage for testing frame indexed accesses.


https://reviews.llvm.org/D26398