[llvm] r287056 - AMDGPU/GCN: Exit early in hazard recognizer if there is no vreg argument

[Jan Vesely via llvm-commits]

Author: jvesely
Date: Tue Nov 15 17:55:15 2016
New Revision: 287056

URL: http://llvm.org/viewvc/llvm-project?rev=287056&view=rev
Log:
AMDGPU/GCN: Exit early in hazard recognizer if there is no vreg argument

wbinvl.* are vector instruction that do not sue vector registers.

v2: check only M?BUF instructions

Differential Revision: https://reviews.llvm.org/D26633

Modified:
    llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
    llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.vol.ll

Modified: llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.cpp?rev=287056&r1=287055&r2=287056&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.cpp Tue Nov 15 17:55:15 2016
@@ -400,6 +400,10 @@ int GCNHazardRecognizer::createsVALUHaza
     VDataRCID = Desc.OpInfo[VDataIdx].RegClass;
 
   if (TII->isMUBUF(MI) || TII->isMTBUF(MI)) {
+    // There is no hazard if the instruction does not use vector regs
+    // (like wbinvl1)
+    if (VDataIdx == -1)
+      return -1;
     // For MUBUF/MTBUF instructions this hazard only exists if the
     // instruction is not using a register in the soffset field.
     const MachineOperand *SOffset =

Modified: llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.vol.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.vol.ll?rev=287056&r1=287055&r2=287056&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.vol.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.vol.ll Tue Nov 15 17:55:15 2016
@@ -7,9 +7,11 @@ declare void @llvm.amdgcn.buffer.wbinvl1
 ; GCN-NEXT: ; BB#0:
 ; CI-NEXT: buffer_wbinvl1_vol ; encoding: [0x00,0x00,0xc0,0xe1,0x00,0x00,0x00,0x00]
 ; VI-NEXT: buffer_wbinvl1_vol ; encoding: [0x00,0x00,0xfc,0xe0,0x00,0x00,0x00,0x00]
-; GCN-NEXT: s_endpgm
+; GCN: s_endpgm
 define void @test_buffer_wbinvl1_vol() #0 {
   call void @llvm.amdgcn.buffer.wbinvl1.vol()
+; This used to crash in hazard recognizer
+  store i8 0, i8 addrspace(1)* undef, align 1
   ret void
 }