[PATCH] D26713: [ppc] Legalize the load of MVT::v4i8 into VSX register

[Guozhi Wei via llvm-commits]

Carrot created this revision.
Carrot added a reviewer: hfinkel.
Carrot added a subscriber: llvm-commits.
Herald added a subscriber: nemanjai.

VSX has an instruction lxsiwax that can load 32bit value into VSX register. That patch makes it known to memory cost model, so the vectorization of the test case in pr30990 is beneficial.


https://reviews.llvm.org/D26713

Files:
  lib/Target/PowerPC/PPCISelLowering.cpp
  test/Transforms/LoopVectorize/PowerPC/pr30990.ll


Index: test/Transforms/LoopVectorize/PowerPC/pr30990.ll
===================================================================
--- test/Transforms/LoopVectorize/PowerPC/pr30990.ll
+++ test/Transforms/LoopVectorize/PowerPC/pr30990.ll
@@ -0,0 +1,36 @@
+; RUN: opt < %s -loop-vectorize -mcpu=pwr8 -mattr=+vsx -force-vector-interleave=1 -vectorizer-maximize-bandwidth=0 -S | FileCheck %s
+
+target triple = "powerpc64-unknown-linux-gnu"
+
+define signext i32 @foo(i8* readonly %ptr, i32 signext %l) {
+entry:
+  %idx.ext = sext i32 %l to i64
+  %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %idx.ext
+  %cmp7 = icmp sgt i32 %l, 0
+  br i1 %cmp7, label %while.body.preheader, label %while.end
+
+while.body.preheader:                             ; preds = %entry
+  br label %while.body
+
+while.body:                                       ; preds = %while.body.preheader, %while.body
+  %count.09 = phi i32 [ %add, %while.body ], [ 0, %while.body.preheader ]
+  %ptr.addr.08 = phi i8* [ %incdec.ptr, %while.body ], [ %ptr, %while.body.preheader ]
+  %0 = load i8, i8* %ptr.addr.08, align 1
+  %cmp1 = icmp slt i8 %0, -64
+  %cond = zext i1 %cmp1 to i32
+  %add = add nsw i32 %cond, %count.09
+  %incdec.ptr = getelementptr inbounds i8, i8* %ptr.addr.08, i64 1
+  %cmp = icmp ult i8* %incdec.ptr, %add.ptr
+  br i1 %cmp, label %while.body, label %while.end.loopexit
+
+while.end.loopexit:                               ; preds = %while.body
+  %add.lcssa = phi i32 [ %add, %while.body ]
+  br label %while.end
+
+while.end:                                        ; preds = %while.end.loopexit, %entry
+  %count.0.lcssa = phi i32 [ 0, %entry ], [ %add.lcssa, %while.end.loopexit ]
+  ret i32 %count.0.lcssa
+
+; CHECK: load <4 x i8>
+; CHECK: icmp slt <4 x i8>
+}
Index: lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- lib/Target/PowerPC/PPCISelLowering.cpp
+++ lib/Target/PowerPC/PPCISelLowering.cpp
@@ -676,6 +676,8 @@
       setOperationAction(ISD::FABS, MVT::v2f64, Legal);
 
       addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
+
+      setLoadExtAction(ISD::EXTLOAD, MVT::v16i8, MVT::v4i8, Custom);
     }
 
     if (Subtarget.hasP8Altivec()) {


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