[PATCH] D23435: AMDGPU: Fix replacing idxen mubuf instructions with addr64

[Matt Arsenault via llvm-commits]

arsenm added inline comments.


================
Comment at: lib/Target/AMDGPU/SIInstrInfo.cpp:2531-2539
+        // NewVaddrLo = SRsrcPtr:sub0 + vaddr
+        BuildMI(MBB, Addr64, DL, get(AMDGPU::V_ADD_I32_e32), AddLo)
+          .addReg(SRsrcPtr, 0, AMDGPU::sub0)
+          .addReg(VAddr->getReg(), 0, VAddr->getSubReg());
+
+        // NewVaddrHi = SRsrcPtr:sub1 + carry
+        BuildMI(MBB, Addr64, DL, get(AMDGPU::V_ADDC_U32_e32), AddHi)
----------------
tstellarAMD wrote:
> The legalization is more complicated because we need to check the stride and tid_enable bits on the resource and do:
> 
> ptr = ptr + (stride * (index + tid))
> 
> I think instead of lowering this, we should try harder to put the base pointer in SGPRs, though I'm not sure of a good way to do that.
Figuring out the TID here is a problem. If it was just the VGPR0 input, a copy could be inserted in the entry block of the input argument to use here, but then we don't know if  the y and z components need to be added, which might not even be enabled inputs yet at this point.


https://reviews.llvm.org/D23435