[llvm] r286960 - [AMDGPU] TableGen: change individual instruction flags to bit type from bits<1>
Sam Kolton via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 15 05:39:07 PST 2016
Author: skolton
Date: Tue Nov 15 07:39:07 2016
New Revision: 286960
URL: http://llvm.org/viewvc/llvm-project?rev=286960&view=rev
Log:
[AMDGPU] TableGen: change individual instruction flags to bit type from bits<1>
Summary: This is needed to be able to use this flags in InstrMappings.
Reviewers: tstellarAMD, vpykhtin
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye
Differential Revision: https://reviews.llvm.org/D26666
Modified:
llvm/trunk/lib/Target/AMDGPU/MIMGInstructions.td
llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
Modified: llvm/trunk/lib/Target/AMDGPU/MIMGInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MIMGInstructions.td?rev=286960&r1=286959&r2=286960&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/MIMGInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/MIMGInstructions.td Tue Nov 15 07:39:07 2016
@@ -155,7 +155,7 @@ multiclass MIMG_Atomic <mimg op, string
class MIMG_Sampler_Helper <bits<7> op, string asm,
RegisterClass dst_rc,
RegisterClass src_rc,
- int wqm,
+ bit wqm,
string dns=""> : MIMG_Helper <
(outs dst_rc:$vdata),
(ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp,
@@ -168,7 +168,7 @@ class MIMG_Sampler_Helper <bits<7> op, s
multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
RegisterClass dst_rc,
- int channels, int wqm> {
+ int channels, bit wqm> {
def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm,
!if(!eq(channels, 1), "AMDGPU", "")>,
MIMG_Mask<asm#"_V1", channels>;
@@ -182,7 +182,7 @@ multiclass MIMG_Sampler_Src_Helper <bits
MIMG_Mask<asm#"_V16", channels>;
}
-multiclass MIMG_Sampler <bits<7> op, string asm, int wqm=0> {
+multiclass MIMG_Sampler <bits<7> op, string asm, bit wqm=0> {
defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, wqm>;
defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, wqm>;
defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, wqm>;
@@ -193,7 +193,7 @@ multiclass MIMG_Sampler_WQM <bits<7> op,
class MIMG_Gather_Helper <bits<7> op, string asm,
RegisterClass dst_rc,
- RegisterClass src_rc, int wqm> : MIMG <
+ RegisterClass src_rc, bit wqm> : MIMG <
(outs dst_rc:$vdata),
(ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp,
dmask:$dmask, unorm:$unorm, GLC:$glc, slc:$slc,
@@ -219,7 +219,7 @@ class MIMG_Gather_Helper <bits<7> op, st
multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
RegisterClass dst_rc,
- int channels, int wqm> {
+ int channels, bit wqm> {
def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
MIMG_Mask<asm#"_V1", channels>;
def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
@@ -232,7 +232,7 @@ multiclass MIMG_Gather_Src_Helper <bits<
MIMG_Mask<asm#"_V16", channels>;
}
-multiclass MIMG_Gather <bits<7> op, string asm, int wqm=0> {
+multiclass MIMG_Gather <bits<7> op, string asm, bit wqm=0> {
defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, wqm>;
defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, wqm>;
defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, wqm>;
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td?rev=286960&r1=286959&r2=286960&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td Tue Nov 15 07:39:07 2016
@@ -15,59 +15,59 @@ class InstSI <dag outs, dag ins, string
list<dag> pattern = []> :
AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
- field bits<1> VM_CNT = 0;
- field bits<1> EXP_CNT = 0;
- field bits<1> LGKM_CNT = 0;
-
- field bits<1> SALU = 0;
- field bits<1> VALU = 0;
-
- field bits<1> SOP1 = 0;
- field bits<1> SOP2 = 0;
- field bits<1> SOPC = 0;
- field bits<1> SOPK = 0;
- field bits<1> SOPP = 0;
-
- field bits<1> VOP1 = 0;
- field bits<1> VOP2 = 0;
- field bits<1> VOP3 = 0;
- field bits<1> VOPC = 0;
- field bits<1> SDWA = 0;
- field bits<1> DPP = 0;
-
- field bits<1> MUBUF = 0;
- field bits<1> MTBUF = 0;
- field bits<1> SMRD = 0;
- field bits<1> DS = 0;
- field bits<1> MIMG = 0;
- field bits<1> FLAT = 0;
+ field bit VM_CNT = 0;
+ field bit EXP_CNT = 0;
+ field bit LGKM_CNT = 0;
+
+ field bit SALU = 0;
+ field bit VALU = 0;
+
+ field bit SOP1 = 0;
+ field bit SOP2 = 0;
+ field bit SOPC = 0;
+ field bit SOPK = 0;
+ field bit SOPP = 0;
+
+ field bit VOP1 = 0;
+ field bit VOP2 = 0;
+ field bit VOP3 = 0;
+ field bit VOPC = 0;
+ field bit SDWA = 0;
+ field bit DPP = 0;
+
+ field bit MUBUF = 0;
+ field bit MTBUF = 0;
+ field bit SMRD = 0;
+ field bit DS = 0;
+ field bit MIMG = 0;
+ field bit FLAT = 0;
// Whether WQM _must_ be enabled for this instruction.
- field bits<1> WQM = 0;
- field bits<1> VGPRSpill = 0;
- field bits<1> SGPRSpill = 0;
+ field bit WQM = 0;
+ field bit VGPRSpill = 0;
+ field bit SGPRSpill = 0;
// This bit tells the assembler to use the 32-bit encoding in case it
// is unable to infer the encoding from the operands.
- field bits<1> VOPAsmPrefer32Bit = 0;
+ field bit VOPAsmPrefer32Bit = 0;
- field bits<1> Gather4 = 0;
+ field bit Gather4 = 0;
// Whether WQM _must_ be disabled for this instruction.
- field bits<1> DisableWQM = 0;
+ field bit DisableWQM = 0;
// Most sopk treat the immediate as a signed 16-bit, however some
// use it as unsigned.
- field bits<1> SOPKZext = 0;
+ field bit SOPKZext = 0;
// This is an s_store_dword* instruction that requires a cache flush
// on wave termination. It is necessary to distinguish from mayStore
// SMEM instructions like the cache flush ones.
- field bits<1> ScalarStore = 0;
+ field bit ScalarStore = 0;
// Whether the operands can be ignored when computing the
// instruction size.
- field bits<1> FixedSize = 0;
+ field bit FixedSize = 0;
// These need to be kept in sync with the enum in SIInstrFlags.
let TSFlags{0} = VM_CNT;
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td?rev=286960&r1=286959&r2=286960&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td Tue Nov 15 07:39:07 2016
@@ -1045,18 +1045,18 @@ multiclass VINTRP_m <bits <2> op, dag ou
def getVOPe64 : InstrMapping {
let FilterClass = "VOP";
let RowFields = ["OpName"];
- let ColFields = ["Size"];
- let KeyCol = ["4"];
- let ValueCols = [["8"]];
+ let ColFields = ["Size", "VOP3"];
+ let KeyCol = ["4", "0"];
+ let ValueCols = [["8", "1"]];
}
// Maps an opcode in e64 form to its e32 equivalent
def getVOPe32 : InstrMapping {
let FilterClass = "VOP";
let RowFields = ["OpName"];
- let ColFields = ["Size"];
- let KeyCol = ["8"];
- let ValueCols = [["4"]];
+ let ColFields = ["Size", "VOP3"];
+ let KeyCol = ["8", "1"];
+ let ValueCols = [["4", "0"]];
}
def getMaskedMIMGOp : InstrMapping {
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