[PATCH] D26585: [AMDGPU] Add wave barrier builtin

[Matt Arsenault via llvm-commits]

arsenm added inline comments.


================
Comment at: lib/Target/AMDGPU/SIInstructions.td:142
+  [(int_amdgcn_wave_barrier)]> {
+  let SALU = 1;
+  let SchedRW = [WriteBarrier];
----------------
I think this shouldn't be set. I think this will end up counting this as 4 bytes instead of 0


================
Comment at: lib/Target/AMDGPU/SIInstructions.td:143
+  let SALU = 1;
+  let SchedRW = [WriteBarrier];
+  let hasSideEffects = 1;
----------------
This should probably be empty and set to hasNoSchedulingInfo like si_mask_branch


Repository:
  rL LLVM

https://reviews.llvm.org/D26585