[PATCH] D26633: AMDGPU/GCN: Exit early in hazard recognizer if there is no vreg argument

[Jan Vesely via llvm-commits]

jvesely updated this revision to Diff 77932.
jvesely added a comment.

v2: only checks for M?BUF instructions.

fixes regression in inserted-wait-states.mir


Repository:
  rL LLVM

https://reviews.llvm.org/D26633

Files:
  lib/Target/AMDGPU/GCNHazardRecognizer.cpp
  test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.vol.ll


Index: test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.vol.ll
===================================================================
--- test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.vol.ll
+++ test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.vol.ll
@@ -7,9 +7,11 @@
 ; GCN-NEXT: ; BB#0:
 ; CI-NEXT: buffer_wbinvl1_vol ; encoding: [0x00,0x00,0xc0,0xe1,0x00,0x00,0x00,0x00]
 ; VI-NEXT: buffer_wbinvl1_vol ; encoding: [0x00,0x00,0xfc,0xe0,0x00,0x00,0x00,0x00]
-; GCN-NEXT: s_endpgm
+; GCN: s_endpgm
 define void @test_buffer_wbinvl1_vol() #0 {
   call void @llvm.amdgcn.buffer.wbinvl1.vol()
+; This used to crash in hazard recognizer
+  store i8 0, i8 addrspace(1)* undef, align 1
   ret void
 }
 
Index: lib/Target/AMDGPU/GCNHazardRecognizer.cpp
===================================================================
--- lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -400,6 +400,10 @@
     VDataRCID = Desc.OpInfo[VDataIdx].RegClass;
 
   if (TII->isMUBUF(MI) || TII->isMTBUF(MI)) {
+    // There is no hazard if the instruction does not use vector regs
+    // (like wbinvl1)
+    if (VDataIdx == -1)
+      return -1;
     // For MUBUF/MTBUF instructions this hazard only exists if the
     // instruction is not using a register in the soffset field.
     const MachineOperand *SOffset =


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