[PATCH] D26648: Clarify semantic of reserved registers.

[Matt Arsenault via llvm-commits]

arsenm added a comment.

In https://reviews.llvm.org/D26648#595163, @MatzeB wrote:

> This is an early patch to get the discussion going. Some things are still missing:
>
> - A bunch of targets violate the superreg rule (e.g. AArch64 reserving XZR but not tuples like %XZR_X0). AArch64, ARM, Hexagon, Mips and PowerPC currently fail the verifier. So far it looks like actual target bugs to me.
> - I think we should add this rule: "If a reserved subregister has subregister at least one subregister (or register unit) must be reserved", yes?


AMDGPU has hit bugs from only reserving the super register before, and not the subregisters


Repository:
  rL LLVM

https://reviews.llvm.org/D26648