[PATCH] D26555: [LV] Keep predicated instructions in the same block

[Michael Kuperstein via llvm-commits]

mkuper added inline comments.


================
Comment at: lib/Transforms/Vectorize/LoopVectorize.cpp:4488
+        for (Instruction *I : ScalarLoopPredInsts) {
+          if (Lane > 0 && Legal->isUniformAfterVectorization(I))
+            continue;
----------------
mssimpso wrote:
> mkuper wrote:
> > What happens in the "Lane == 0 && Legal->isUniformAfterVectorization(I)" case?
> > I'm having a bit of trouble imagining what the code ends up looking.
> This loop is collecting in VectorLoopPredInsts the scalarized instructions we produced in scalarizeInstruction. It then predicates all the scalarized instructions for a given unroll part and vector lane. If an instruction is uniform-after-vectorization we only generate values for Lane zero during scalarization, and getScalarValue asserts if we try to get a value for a Lane > 0.
> 
> However, as I'm thinking about this, I don't think we can ever end up with an instruction that requires predication that is also marked uniform-after-vectorization. Unless I'm missing something, we should probably just remove this if condition. What do you think?
> However, as I'm thinking about this, I don't think we can ever end up with an instruction that requires predication that is also marked uniform-after-vectorization. Unless I'm missing something, we should probably just remove this if condition. What do you think?

Yes, that's why I was having trouble imagining it. Couldn't figure out what a uniform-after-vectorization predicated instruction looks like.

I think we should remove this, and have an assert somewhere to make sure it really doesn't happen. (If we find out that does happen, I guess it's some edge-case we're not thinking about, so I'm not sure this code would do the right thing anyway.)


https://reviews.llvm.org/D26555