[llvm] r286829 - [PPC] add intrinsics for vec extract exp/significand and vec test data class.
Sean Fertile via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 14 06:42:37 PST 2016
Author: sfertile
Date: Mon Nov 14 08:42:37 2016
New Revision: 286829
URL: http://llvm.org/viewvc/llvm-project?rev=286829&view=rev
Log:
[PPC] add intrinsics for vec extract exp/significand and vec test data class.
Differential Revision: https://reviews.llvm.org/D26272
Modified:
llvm/trunk/include/llvm/IR/IntrinsicsPowerPC.td
llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td
llvm/trunk/test/CodeGen/PowerPC/vsx-p9.ll
Modified: llvm/trunk/include/llvm/IR/IntrinsicsPowerPC.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsPowerPC.td?rev=286829&r1=286828&r2=286829&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IR/IntrinsicsPowerPC.td (original)
+++ llvm/trunk/include/llvm/IR/IntrinsicsPowerPC.td Mon Nov 14 08:42:37 2016
@@ -849,6 +849,24 @@ def int_ppc_vsx_xvcvdpsp :
def int_ppc_vsx_xvcvsphp :
PowerPC_VSX_Intrinsic<"xvcvsphp", [llvm_v4f32_ty],
[llvm_v4f32_ty], [IntrNoMem]>;
+def int_ppc_vsx_xvxexpdp :
+ PowerPC_VSX_Intrinsic<"xvxexpdp", [llvm_v2i64_ty],
+ [llvm_v2f64_ty], [IntrNoMem]>;
+def int_ppc_vsx_xvxexpsp :
+ PowerPC_VSX_Intrinsic<"xvxexpsp", [llvm_v4i32_ty],
+ [llvm_v4f32_ty], [IntrNoMem]>;
+def int_ppc_vsx_xvxsigdp :
+ PowerPC_VSX_Intrinsic<"xvxsigdp", [llvm_v2i64_ty],
+ [llvm_v2f64_ty], [IntrNoMem]>;
+def int_ppc_vsx_xvxsigsp :
+ PowerPC_VSX_Intrinsic<"xvxsigsp", [llvm_v4i32_ty],
+ [llvm_v4f32_ty], [IntrNoMem]>;
+def int_ppc_vsx_xvtstdcdp :
+ PowerPC_VSX_Intrinsic<"xvtstdcdp", [llvm_v2i64_ty],
+ [llvm_v2f64_ty, llvm_i32_ty], [IntrNoMem]>;
+def int_ppc_vsx_xvtstdcsp :
+ PowerPC_VSX_Intrinsic<"xvtstdcsp", [llvm_v4i32_ty],
+ [llvm_v4f32_ty,llvm_i32_ty], [IntrNoMem]>;
}
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td?rev=286829&r1=286828&r2=286829&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td Mon Nov 14 08:42:37 2016
@@ -2206,10 +2206,18 @@ let AddedComplexity = 400, Predicates =
IIC_VecFP, [(set v4f32: $XT,(int_ppc_vsx_xviexpsp v4i32:$XA, v4i32:$XB))]>;
// Vector Extract Exponent/Significand DP/SP
- def XVXEXPDP : XX2_XT6_XO5_XB6<60, 0, 475, "xvxexpdp", vsrc, []>;
- def XVXEXPSP : XX2_XT6_XO5_XB6<60, 8, 475, "xvxexpsp", vsrc, []>;
- def XVXSIGDP : XX2_XT6_XO5_XB6<60, 1, 475, "xvxsigdp", vsrc, []>;
- def XVXSIGSP : XX2_XT6_XO5_XB6<60, 9, 475, "xvxsigsp", vsrc, []>;
+ def XVXEXPDP : XX2_XT6_XO5_XB6<60, 0, 475, "xvxexpdp", vsrc,
+ [(set v2i64: $XT,
+ (int_ppc_vsx_xvxexpdp v2f64:$XB))]>;
+ def XVXEXPSP : XX2_XT6_XO5_XB6<60, 8, 475, "xvxexpsp", vsrc,
+ [(set v4i32: $XT,
+ (int_ppc_vsx_xvxexpsp v4f32:$XB))]>;
+ def XVXSIGDP : XX2_XT6_XO5_XB6<60, 1, 475, "xvxsigdp", vsrc,
+ [(set v2i64: $XT,
+ (int_ppc_vsx_xvxsigdp v2f64:$XB))]>;
+ def XVXSIGSP : XX2_XT6_XO5_XB6<60, 9, 475, "xvxsigsp", vsrc,
+ [(set v4i32: $XT,
+ (int_ppc_vsx_xvxsigsp v4f32:$XB))]>;
//===--------------------------------------------------------------------===//
@@ -2230,10 +2238,14 @@ let AddedComplexity = 400, Predicates =
let UseVSXReg = 1 in {
def XVTSTDCSP : XX2_RD6_DCMX7_RS6<60, 13, 5,
(outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB),
- "xvtstdcsp $XT, $XB, $DCMX", IIC_VecFP, []>;
+ "xvtstdcsp $XT, $XB, $DCMX", IIC_VecFP,
+ [(set v4i32: $XT,
+ (int_ppc_vsx_xvtstdcsp v4f32:$XB, imm:$DCMX))]>;
def XVTSTDCDP : XX2_RD6_DCMX7_RS6<60, 15, 5,
(outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB),
- "xvtstdcdp $XT, $XB, $DCMX", IIC_VecFP, []>;
+ "xvtstdcdp $XT, $XB, $DCMX", IIC_VecFP,
+ [(set v2i64: $XT,
+ (int_ppc_vsx_xvtstdcdp v2f64:$XB, imm:$DCMX))]>;
} // UseVSXReg = 1
//===--------------------------------------------------------------------===//
Modified: llvm/trunk/test/CodeGen/PowerPC/vsx-p9.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vsx-p9.ll?rev=286829&r1=286828&r2=286829&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vsx-p9.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/vsx-p9.ll Mon Nov 14 08:42:37 2016
@@ -260,4 +260,75 @@ declare <4 x i32> @llvm.ppc.altivec.vrlw
; Function Attrs: nounwind readnone
declare <2 x i64> @llvm.ppc.altivec.vrldnm(<2 x i64>, <2 x i64>)
+define <4 x i32> @testXVXEXPSP(<4 x float> %a) {
+entry:
+ %0 = tail call <4 x i32> @llvm.ppc.vsx.xvxexpsp(<4 x float> %a)
+ ret <4 x i32> %0
+; CHECK-LABEL: testXVXEXPSP
+; CHECK: xvxexpsp 34, 34
+; CHECK: blr
+}
+; Function Attrs: nounwind readnone
+declare <4 x i32> @llvm.ppc.vsx.xvxexpsp(<4 x float>)
+
+; Function Attrs: nounwind readnone
+define <2 x i64> @testXVXEXPDP(<2 x double> %a) {
+entry:
+ %0 = tail call <2 x i64> @llvm.ppc.vsx.xvxexpdp(<2 x double> %a)
+ ret <2 x i64> %0
+; CHECK-LABEL: testXVXEXPDP
+; CHECK xvxexpdp 34, 34
+; CHECK blr
+}
+; Function Attrs: nounwind readnone
+declare <2 x i64>@llvm.ppc.vsx.xvxexpdp(<2 x double>)
+
+; Function Attrs: nounwind readnone
+define <4 x i32> @testXVXSIGSP(<4 x float> %a) {
+entry:
+ %0 = tail call <4 x i32> @llvm.ppc.vsx.xvxsigsp(<4 x float> %a)
+ ret <4 x i32> %0
+; CHECK-LABEL: testXVXSIGSP
+; CHECK xvxsigsp 34, 34
+; CHECK blr
+}
+; Function Attrs: nounwind readnone
+declare <4 x i32> @llvm.ppc.vsx.xvxsigsp(<4 x float>)
+
+; Function Attrs: nounwind readnone
+define <2 x i64> @testXVXSIGDP(<2 x double> %a) {
+entry:
+ %0 = tail call <2 x i64> @llvm.ppc.vsx.xvxsigdp(<2 x double> %a)
+ ret <2 x i64> %0
+; CHECK-LABEL: testXVXSIGDP
+; CHECK xvxsigdp 34, 34
+; CHECK blr
+}
+; Function Attrs: nounwind readnone
+declare <2 x i64> @llvm.ppc.vsx.xvxsigdp(<2 x double>)
+
+; Function Attrs: nounwind readnone
+define <4 x i32> @testXVTSTDCSP(<4 x float> %a) {
+entry:
+ %0 = tail call <4 x i32> @llvm.ppc.vsx.xvtstdcsp(<4 x float> %a, i32 127)
+ ret <4 x i32> %0
+; CHECK-LABEL: testXVTSTDCSP
+; CHECK: xvtstdcsp 34, 34, 127
+; CHECK: blr
+}
+; Function Attrs: nounwind readnone
+declare <4 x i32> @llvm.ppc.vsx.xvtstdcsp(<4 x float> %a, i32 %b)
+
+; Function Attrs: nounwind readnone
+define <2 x i64> @testXVTSTDCDP(<2 x double> %a) {
+entry:
+ %0 = tail call <2 x i64> @llvm.ppc.vsx.xvtstdcdp(<2 x double> %a, i32 127)
+ ret <2 x i64> %0
+; CHECK-LABEL: testXVTSTDCDP
+; CHECK: xvtstdcdp 34, 34, 127
+; CHECK: blr
+}
+; Function Attrs: nounwind readnone
+declare <2 x i64> @llvm.ppc.vsx.xvtstdcdp(<2 x double> %a, i32 %b)
+
declare void @sink(...)
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