[llvm] r286656 - Revert "(origin/master, origin/HEAD) MachineScheduler/ScheduleDAG: Add support to skipping a node."

[Matthias Braun via llvm-commits]

Author: matze
Date: Fri Nov 11 16:39:50 2016
New Revision: 286656

URL: http://llvm.org/viewvc/llvm-project?rev=286656&view=rev
Log:
Revert "(origin/master, origin/HEAD) MachineScheduler/ScheduleDAG: Add support to skipping a node."

Revert accidentally committed change.

This reverts commit r286655.

Modified:
    llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h
    llvm/trunk/lib/CodeGen/MachineScheduler.cpp
    llvm/trunk/lib/CodeGen/ScheduleDAG.cpp

Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h?rev=286656&r1=286655&r2=286656&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h Fri Nov 11 16:39:50 2016
@@ -289,7 +289,6 @@ namespace llvm {
     bool isCloned         : 1;          // True if this node has been cloned.
     bool isUnbuffered     : 1;          // Uses an unbuffered resource.
     bool hasReservedResource : 1;       // Uses a reserved resource.
-    bool skip             : 1;          ///< Ignore/Skip this node.
     Sched::Preference SchedulingPref;   // Scheduling preference.
 
   private:
@@ -315,7 +314,7 @@ namespace llvm {
         hasPhysRegUses(false), hasPhysRegDefs(false), hasPhysRegClobbers(false),
         isPending(false), isAvailable(false), isScheduled(false),
         isScheduleHigh(false), isScheduleLow(false), isCloned(false),
-        isUnbuffered(false), hasReservedResource(false), skip(false),
+        isUnbuffered(false), hasReservedResource(false),
         SchedulingPref(Sched::None), isDepthCurrent(false),
         isHeightCurrent(false), Depth(0), Height(0), TopReadyCycle(0),
         BotReadyCycle(0), CopyDstRC(nullptr), CopySrcRC(nullptr) {}
@@ -331,7 +330,7 @@ namespace llvm {
         hasPhysRegUses(false), hasPhysRegDefs(false), hasPhysRegClobbers(false),
         isPending(false), isAvailable(false), isScheduled(false),
         isScheduleHigh(false), isScheduleLow(false), isCloned(false),
-        isUnbuffered(false), hasReservedResource(false), skip(false),
+        isUnbuffered(false), hasReservedResource(false),
         SchedulingPref(Sched::None), isDepthCurrent(false),
         isHeightCurrent(false), Depth(0), Height(0), TopReadyCycle(0),
         BotReadyCycle(0), CopyDstRC(nullptr), CopySrcRC(nullptr) {}
@@ -346,7 +345,7 @@ namespace llvm {
         hasPhysRegUses(false), hasPhysRegDefs(false), hasPhysRegClobbers(false),
         isPending(false), isAvailable(false), isScheduled(false),
         isScheduleHigh(false), isScheduleLow(false), isCloned(false),
-        isUnbuffered(false), hasReservedResource(false), skip(false),
+        isUnbuffered(false), hasReservedResource(false),
         SchedulingPref(Sched::None), isDepthCurrent(false),
         isHeightCurrent(false), Depth(0), Height(0), TopReadyCycle(0),
         BotReadyCycle(0), CopyDstRC(nullptr), CopySrcRC(nullptr) {}

Modified: llvm/trunk/lib/CodeGen/MachineScheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineScheduler.cpp?rev=286656&r1=286655&r2=286656&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineScheduler.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineScheduler.cpp Fri Nov 11 16:39:50 2016
@@ -707,7 +707,6 @@ void ScheduleDAGMI::schedule() {
     DEBUG(dbgs() << "** ScheduleDAGMI::schedule picking next node\n");
     SUnit *SU = SchedImpl->pickNode(IsTopNode);
     if (!SU) break;
-    assert(!SU->skip);
 
     assert(!SU->isScheduled && "Node already scheduled");
     if (!checkSchedLimit())
@@ -765,8 +764,6 @@ findRootsAndBiasEdges(SmallVectorImpl<SU
                       SmallVectorImpl<SUnit*> &BotRoots) {
   for (std::vector<SUnit>::iterator
          I = SUnits.begin(), E = SUnits.end(); I != E; ++I) {
-    if (I->skip)
-      continue;
     SUnit *SU = &(*I);
     assert(!SU->isBoundaryNode() && "Boundary node should not be in SUnits");
 
@@ -1521,8 +1518,6 @@ void BaseMemOpClusterMutation::apply(Sch
   SmallVector<SmallVector<SUnit*,4>, 32> StoreChainDependents;
   for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
     SUnit *SU = &DAG->SUnits[Idx];
-    if (SU->skip)
-      continue;
     if ((IsLoad && !SU->getInstr()->mayLoad()) ||
         (!IsLoad && !SU->getInstr()->mayStore()))
       continue;
@@ -1815,8 +1810,6 @@ void CopyConstrain::apply(ScheduleDAGIns
 
   for (unsigned Idx = 0, End = DAG->SUnits.size(); Idx != End; ++Idx) {
     SUnit *SU = &DAG->SUnits[Idx];
-    if (SU->skip)
-      continue;
     if (!SU->getInstr()->isCopy())
       continue;
 

Modified: llvm/trunk/lib/CodeGen/ScheduleDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAG.cpp?rev=286656&r1=286655&r2=286656&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/ScheduleDAG.cpp Fri Nov 11 16:39:50 2016
@@ -329,10 +329,6 @@ void SUnit::dump(const ScheduleDAG *G) c
 
 void SUnit::dumpAll(const ScheduleDAG *G) const {
   dump(G);
-  if (skip) {
-    dbgs() << "  Skipped\n";
-    return;
-  }
 
   dbgs() << "  # preds left       : " << NumPredsLeft << "\n";
   dbgs() << "  # succs left       : " << NumSuccsLeft << "\n";