[PATCH] D26561: [AArch64] Split 0 vector stores into scalar store pairs.
Geoff Berry via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 11 13:33:16 PST 2016
gberry created this revision.
gberry added reviewers: t.p.northover, mcrosier, MatzeB, jmolloy.
gberry added a subscriber: llvm-commits.
Herald added subscribers: rengolin, aemerson.
Replace a splat of zeros to a vector store by scalar stores of WZR/XZR.
The load store optimizer pass will merge them to store pair stores.
This should be better than a movi to create the vector zero followed by
a vector store if the zero constant is not re-used, since one
instructions and one register live range will be removed.
For example, the final generated code should be:
stp xzr, xzr, [x0]
instead of:
movi v0.2d, #0
str q0, [x0]
https://reviews.llvm.org/D26561
Files:
lib/Target/AArch64/AArch64ISelLowering.cpp
test/CodeGen/AArch64/arm64-misched-basic-A53.ll
test/CodeGen/AArch64/ldst-opt.ll
test/CodeGen/AArch64/ldst-paired-aliasing.ll
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D26561.77663.patch
Type: text/x-patch
Size: 9377 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20161111/16ca166a/attachment.bin>
More information about the llvm-commits
mailing list