[PATCH] D26547: [PPC] add intrinsics mapping to the extractuw/insertw instructiosn

[Sean Fertile via llvm-commits]

sfertile created this revision.
sfertile added reviewers: kbarton, amehsan, lei, jtony, syzaara, nemanjai.
sfertile added subscribers: llvm-commits, echristo.
sfertile set the repository for this revision to rL LLVM.

Adds intrinsics mapping to the xxextractuw/xxinsertw instructions.

The int_ppc_vsx_xxextractuw pattern expansion requires 'casting' the out register from a f64:vsfrc to a VSRC since the altivec functionality I am trying to implement requires a return value of v2i64 with the second element zeroed out.


Repository:
  rL LLVM

https://reviews.llvm.org/D26547

Files:
  include/llvm/IR/IntrinsicsPowerPC.td
  lib/Target/PowerPC/PPCInstrVSX.td
  test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll


Index: test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll
===================================================================
--- test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll
+++ test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll
@@ -990,3 +990,21 @@
   %vecins = insertelement <4 x i32> %a, i32 %i, i32 %el
   ret <4 x i32> %vecins
 }
+define <4 x i32> @intrinsicInsertTest(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL:intrinsicInsertTest
+; CHECK: xxinsertw 34, 35, 3
+; CHECK: blr
+  %ans = tail call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> %a, <4 x i32> %b, i32 3)
+  ret <4 x i32> %ans
+}
+declare <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32>, <4 x i32>, i32)
+define <2 x i64> @intrinsicExtractTest(<4 x i32> %a) {
+entry:
+; CHECK-LABEL: intrinsicExtractTest
+; CHECK: xxextractuw 0, 34, 5
+; CHECK: blr
+  %ans = tail call <2 x i64> @llvm.ppc.vsx.xxextractuw(<4 x i32> %a, i32 5)
+  ret <2 x i64> %ans
+}
+declare <2 x i64>  @llvm.ppc.vsx.xxextractuw(<4 x i32>, i32)
Index: lib/Target/PowerPC/PPCInstrVSX.td
===================================================================
--- lib/Target/PowerPC/PPCInstrVSX.td
+++ lib/Target/PowerPC/PPCInstrVSX.td
@@ -2201,6 +2201,13 @@
   def XVXSIGDP : XX2_XT6_XO5_XB6<60,  1, 475, "xvxsigdp", vsrc, []>;
   def XVXSIGSP : XX2_XT6_XO5_XB6<60,  9, 475, "xvxsigsp", vsrc, []>;
 
+  // Extra patterns for matching insertw/extractw instructions
+  def : Pat<(v4i32 (int_ppc_vsx_xxinsertw v4i32:$A, v4i32:$B, imm:$UIM)),
+            (v4i32 (XXINSERTW $A, $B, imm:$UIM))>;
+  def : Pat<(v2i64 (int_ppc_vsx_xxextractuw v4i32:$A, imm:$IMM)),
+            (v2i64 (COPY_TO_REGCLASS
+               (v2f64 (COPY_TO_REGCLASS
+                 (f64 (XXEXTRACTUW $A, imm:$IMM)), VSRC)), VSRC))>;
   //===--------------------------------------------------------------------===//
 
   // Test Data Class SP/DP/QP
Index: include/llvm/IR/IntrinsicsPowerPC.td
===================================================================
--- include/llvm/IR/IntrinsicsPowerPC.td
+++ include/llvm/IR/IntrinsicsPowerPC.td
@@ -806,6 +806,13 @@
 def int_ppc_vsx_xviexpsp :
       PowerPC_VSX_Intrinsic<"xviexpsp",[llvm_v4f32_ty],
                             [llvm_v4i32_ty, llvm_v4i32_ty],[IntrNoMem]>;
+def int_ppc_vsx_xxextractuw :
+      PowerPC_VSX_Intrinsic<"xxextractuw",[llvm_v2i64_ty],
+                            [llvm_v4i32_ty,llvm_i32_ty], [IntrNoMem]>;
+def int_ppc_vsx_xxinsertw :
+      PowerPC_VSX_Intrinsic<"xxinsertw",[llvm_v4i32_ty],
+                            [llvm_v4i32_ty,llvm_v4i32_ty,llvm_i32_ty],
+                            [IntrNoMem]>;
 }
 
 //===----------------------------------------------------------------------===//


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