[llvm] r286582 - [SelectionDAG] Add support for vector demandedelts in BSWAP opcodes

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Fri Nov 11 05:51:29 2016
New Revision: 286582

URL: http://llvm.org/viewvc/llvm-project?rev=286582&view=rev
Log:
[SelectionDAG] Add support for vector demandedelts in BSWAP opcodes

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/test/CodeGen/X86/known-bits-vector.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=286582&r1=286581&r2=286582&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Nov 11 05:51:29 2016
@@ -2575,7 +2575,8 @@ void SelectionDAG::computeKnownBits(SDVa
     break;
   }
   case ISD::BSWAP: {
-    computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
+    computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, DemandedElts,
+                     Depth + 1);
     KnownZero = KnownZero2.byteSwap();
     KnownOne = KnownOne2.byteSwap();
     break;

Modified: llvm/trunk/test/CodeGen/X86/known-bits-vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/known-bits-vector.ll?rev=286582&r1=286581&r2=286582&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/known-bits-vector.ll (original)
+++ llvm/trunk/test/CodeGen/X86/known-bits-vector.ll Fri Nov 11 05:51:29 2016
@@ -309,16 +309,12 @@ define <4 x i32> @knownbits_mask_srem_sh
 define <4 x i32> @knownbits_mask_bswap_shuffle_shl(<4 x i32> %a0) nounwind {
 ; X32-LABEL: knownbits_mask_bswap_shuffle_shl:
 ; X32:       # BB#0:
-; X32-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
-; X32-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[3,2,1,0,3,2,1,0,15,14,13,12,15,14,13,12]
-; X32-NEXT:    vpslld $22, %xmm0, %xmm0
+; X32-NEXT:    vxorps %xmm0, %xmm0, %xmm0
 ; X32-NEXT:    retl
 ;
 ; X64-LABEL: knownbits_mask_bswap_shuffle_shl:
 ; X64:       # BB#0:
-; X64-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
-; X64-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[3,2,1,0,3,2,1,0,15,14,13,12,15,14,13,12]
-; X64-NEXT:    vpslld $22, %xmm0, %xmm0
+; X64-NEXT:    vxorps %xmm0, %xmm0, %xmm0
 ; X64-NEXT:    retq
   %1 = and <4 x i32> %a0, <i32 32767, i32 -1, i32 -1, i32 32767>
   %2 = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %1)