[llvm] r286183 - GlobalISel: constrain PHI registers on AArch64.

[Quentin Colombet via llvm-commits]

Hi Tim,

Could we have this handled by the generic pass?
I expect all targets to encounter the same problem.

Cheers,
-Quentin
> On Nov 7, 2016, at 4:34 PM, Tim Northover via llvm-commits <llvm-commits at lists.llvm.org> wrote:
> 
> Author: tnorthover
> Date: Mon Nov  7 18:34:06 2016
> New Revision: 286183
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=286183&view=rev
> Log:
> GlobalISel: constrain PHI registers on AArch64.
> 
> Self-referencing PHI nodes need their destination operands to be constrained
> because nothing else is likely to do so. For now we just pick a register class
> naively.
> 
> Patch mostly by Ahmed again.
> 
> Modified:
>    llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
>    llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
> 
> Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=286183&r1=286182&r2=286183&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Mon Nov  7 18:34:06 2016
> @@ -484,10 +484,40 @@ bool AArch64InstructionSelector::select(
> 
>     if (Opcode ==  TargetOpcode::LOAD_STACK_GUARD)
>       return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
> -    else if (I.isCopy())
> +
> +    if (Opcode == TargetOpcode::PHI) {
> +      const unsigned DefReg = I.getOperand(0).getReg();
> +      const LLT DefTy = MRI.getType(DefReg);
> +
> +      const TargetRegisterClass *DefRC = nullptr;
> +      if (TargetRegisterInfo::isPhysicalRegister(DefReg)) {
> +        DefRC = TRI.getRegClass(DefReg);
> +      } else {
> +        const RegClassOrRegBank &RegClassOrBank =
> +            MRI.getRegClassOrRegBank(DefReg);
> +
> +        DefRC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>();
> +        if (!DefRC) {
> +          if (!DefTy.isValid()) {
> +            DEBUG(dbgs() << "PHI operand has no type, not a gvreg?\n");
> +            return false;
> +          }
> +          const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>();
> +          DefRC = getRegClassForTypeOnBank(DefTy, RB, RBI);
> +          if (!DefRC) {
> +            DEBUG(dbgs() << "PHI operand has unexpected size/bank\n");
> +            return false;
> +          }
> +        }
> +      }
> +
> +      return RBI.constrainGenericRegister(DefReg, *DefRC, MRI);
> +    }
> +
> +    if (I.isCopy())
>       return selectCopy(I, TII, MRI, TRI, RBI);
> -    else
> -      return true;
> +
> +    return true;
>   }
> 
> 
> 
> Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir?rev=286183&r1=286182&r2=286183&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir (original)
> +++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir Mon Nov  7 18:34:06 2016
> @@ -147,6 +147,9 @@
> 
>   define void @icmp() { ret void }
>   define void @fcmp() { ret void }
> +
> +  define void @phi() { ret void }
> +
> ...
> 
> ---
> @@ -2834,3 +2837,40 @@ body:             |
>     %3(s1) = G_FCMP floatpred(uge), %2, %2
> 
> ...
> +
> +---
> +# CHECK-LABEL: name: phi
> +name:            phi
> +legalized:       true
> +regBankSelected: true
> +tracksRegLiveness: true
> +
> +# CHECK:      registers:
> +# CHECK-NEXT:  - { id: 0, class: fpr32 }
> +# CHECK-NEXT:  - { id: 1, class: gpr32 }
> +# CHECK-NEXT:  - { id: 2, class: fpr32 }
> +registers:
> +  - { id: 0, class: fpr }
> +  - { id: 1, class: gpr }
> +  - { id: 2, class: fpr }
> +
> +# CHECK:  body:
> +# CHECK:    bb.1:
> +# CHECK:      %2 = PHI %0, %bb.0, %2, %bb.1
> +
> +body:             |
> +  bb.0:
> +    liveins: %s0, %w0
> +    successors: %bb.1
> +    %0(s32) = COPY %s0
> +    %1(s1) = COPY %w0
> +
> +  bb.1:
> +    successors: %bb.1, %bb.2
> +    %2(s32) = PHI %0, %bb.0, %2, %bb.1
> +    G_BRCOND %1, %bb.1
> +
> +  bb.2:
> +    %s0 = COPY %2
> +    RET_ReallyLR implicit %s0
> +...
> 
> 
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