[llvm] r286511 - [X86] Add knownbits vector ADD test

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Thu Nov 10 14:21:04 PST 2016


Author: rksimon
Date: Thu Nov 10 16:21:04 2016
New Revision: 286511

URL: http://llvm.org/viewvc/llvm-project?rev=286511&view=rev
Log:
[X86] Add knownbits vector ADD test

Modified:
    llvm/trunk/test/CodeGen/X86/known-bits-vector.ll

Modified: llvm/trunk/test/CodeGen/X86/known-bits-vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/known-bits-vector.ll?rev=286511&r1=286510&r2=286511&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/known-bits-vector.ll (original)
+++ llvm/trunk/test/CodeGen/X86/known-bits-vector.ll Thu Nov 10 16:21:04 2016
@@ -204,6 +204,23 @@ define <4 x i32> @knownbits_mask_trunc_s
   ret <4 x i32> %4
 }
 
+define <4 x i32> @knownbits_add_lshr(<4 x i32> %a0, <4 x i32> %a1) nounwind {
+; X32-LABEL: knownbits_add_lshr:
+; X32:       # BB#0:
+; X32-NEXT:    vxorps %xmm0, %xmm0, %xmm0
+; X32-NEXT:    retl
+;
+; X64-LABEL: knownbits_add_lshr:
+; X64:       # BB#0:
+; X64-NEXT:    vxorps %xmm0, %xmm0, %xmm0
+; X64-NEXT:    retq
+  %1 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>
+  %2 = and <4 x i32> %a1, <i32 32767, i32 32767, i32 32767, i32 32767>
+  %3 = add <4 x i32> %1, %2
+  %4 = lshr <4 x i32> %3, <i32 17, i32 17, i32 17, i32 17>
+  ret <4 x i32> %4
+}
+
 define <4 x i32> @knownbits_sub_lshr(<4 x i32> %a0) nounwind {
 ; X32-LABEL: knownbits_sub_lshr:
 ; X32:       # BB#0:




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