[llvm] r286508 - [X86] Add knownbits vector SUB test

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Thu Nov 10 15:50:23 2016
New Revision: 286508

URL: http://llvm.org/viewvc/llvm-project?rev=286508&view=rev
Log:
[X86] Add knownbits vector SUB test

Modified:
    llvm/trunk/test/CodeGen/X86/known-bits-vector.ll

Modified: llvm/trunk/test/CodeGen/X86/known-bits-vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/known-bits-vector.ll?rev=286508&r1=286507&r2=286508&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/known-bits-vector.ll (original)
+++ llvm/trunk/test/CodeGen/X86/known-bits-vector.ll Thu Nov 10 15:50:23 2016
@@ -203,3 +203,26 @@ define <4 x i32> @knownbits_mask_trunc_s
   %4 = shl <4 x i32> %3, <i32 22, i32 22, i32 22, i32 22>
   ret <4 x i32> %4
 }
+
+define <4 x i32> @knownbits_sub_lshr(<4 x i32> %a0) nounwind {
+; X32-LABEL: knownbits_sub_lshr:
+; X32:       # BB#0:
+; X32-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-NEXT:    vmovdqa {{.*#+}} xmm1 = [255,255,255,255]
+; X32-NEXT:    vpsubd %xmm0, %xmm1, %xmm0
+; X32-NEXT:    vpsrld $22, %xmm0, %xmm0
+; X32-NEXT:    retl
+;
+; X64-LABEL: knownbits_sub_lshr:
+; X64:       # BB#0:
+; X64-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; X64-NEXT:    vmovdqa {{.*#+}} xmm1 = [255,255,255,255]
+; X64-NEXT:    vpsubd %xmm0, %xmm1, %xmm0
+; X64-NEXT:    vpsrld $22, %xmm0, %xmm0
+; X64-NEXT:    retq
+  %1 = and <4 x i32> %a0, <i32 15, i32 15, i32 15, i32 15>
+  %2 = sub <4 x i32> <i32 255, i32 255, i32 255, i32 255>, %1
+  %3 = lshr <4 x i32> %2, <i32 22, i32 22, i32 22, i32 22>
+  ret <4 x i32> %3
+
+}