[llvm] r286377 - [Hexagon] Separate Hexagon subreg indices for different register classes
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 9 08:19:08 PST 2016
Author: kparzysz
Date: Wed Nov 9 10:19:08 2016
New Revision: 286377
URL: http://llvm.org/viewvc/llvm-project?rev=286377&view=rev
Log:
[Hexagon] Separate Hexagon subreg indices for different register classes
For pairs of 32-bit registers: isub_lo, isub_hi.
For pairs of vector registers: vsub_lo, vsub_hi.
Add generic subreg indices: ps_sub_lo, ps_sub_hi, and a function
HexagonRegisterInfo::getHexagonSubRegIndex(RegClass, GenericSubreg)
that returns the appropriate subreg index for RegClass.
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp
llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp
llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp
llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp
llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp
llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp
llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp
llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp
llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp
llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp
llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsDerived.td
llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsV60.td
llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td
llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp
llvm/trunk/lib/Target/Hexagon/HexagonRDFOpt.cpp
llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp
llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.h
llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td
llvm/trunk/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp
llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp
llvm/trunk/test/CodeGen/Hexagon/expand-condsets-def-undef.mir
llvm/trunk/test/CodeGen/Hexagon/regalloc-bad-undef.mir
Modified: llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp?rev=286377&r1=286376&r2=286377&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp Wed Nov 9 10:19:08 2016
@@ -152,8 +152,8 @@ bool HexagonAsmPrinter::PrintAsmOperand(
// This should be an assert in the frontend.
if (Hexagon::DoubleRegsRegClass.contains(RegNumber))
RegNumber = TRI->getSubReg(RegNumber, ExtraCode[0] == 'L' ?
- Hexagon::subreg_loreg :
- Hexagon::subreg_hireg);
+ Hexagon::isub_lo :
+ Hexagon::isub_hi);
OS << HexagonInstPrinter::getRegisterName(RegNumber);
return false;
}
@@ -414,8 +414,8 @@ void HexagonAsmPrinter::HexagonProcessIn
TmpInst.setOpcode(Hexagon::A2_combinew);
TmpInst.addOperand(MappedInst.getOperand(0));
MCOperand &MO1 = MappedInst.getOperand(1);
- unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::subreg_hireg);
- unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::subreg_loreg);
+ unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi);
+ unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::isub_lo);
// Add a new operand for the second register in the pair.
TmpInst.addOperand(MCOperand::createReg(High));
TmpInst.addOperand(MCOperand::createReg(Low));
@@ -487,8 +487,8 @@ void HexagonAsmPrinter::HexagonProcessIn
// Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
case Hexagon::A2_tfrp: {
MCOperand &MO = MappedInst.getOperand(1);
- unsigned High = RI->getSubReg(MO.getReg(), Hexagon::subreg_hireg);
- unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::subreg_loreg);
+ unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
+ unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
MO.setReg(High);
// Add a new operand for the second register in the pair.
MappedInst.addOperand(MCOperand::createReg(Low));
@@ -499,8 +499,8 @@ void HexagonAsmPrinter::HexagonProcessIn
case Hexagon::A2_tfrpt:
case Hexagon::A2_tfrpf: {
MCOperand &MO = MappedInst.getOperand(2);
- unsigned High = RI->getSubReg(MO.getReg(), Hexagon::subreg_hireg);
- unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::subreg_loreg);
+ unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
+ unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
MO.setReg(High);
// Add a new operand for the second register in the pair.
MappedInst.addOperand(MCOperand::createReg(Low));
@@ -512,8 +512,8 @@ void HexagonAsmPrinter::HexagonProcessIn
case Hexagon::A2_tfrptnew:
case Hexagon::A2_tfrpfnew: {
MCOperand &MO = MappedInst.getOperand(2);
- unsigned High = RI->getSubReg(MO.getReg(), Hexagon::subreg_hireg);
- unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::subreg_loreg);
+ unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi);
+ unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo);
MO.setReg(High);
// Add a new operand for the second register in the pair.
MappedInst.addOperand(MCOperand::createReg(Low));
Modified: llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp?rev=286377&r1=286376&r2=286377&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp Wed Nov 9 10:19:08 2016
@@ -175,7 +175,8 @@ namespace {
static bool replaceSubWithSub(unsigned OldR, unsigned OldSR,
unsigned NewR, unsigned NewSR, MachineRegisterInfo &MRI);
static bool parseRegSequence(const MachineInstr &I,
- BitTracker::RegisterRef &SL, BitTracker::RegisterRef &SH);
+ BitTracker::RegisterRef &SL, BitTracker::RegisterRef &SH,
+ const MachineRegisterInfo &MRI);
static bool getUsedBitsInStore(unsigned Opc, BitVector &Bits,
uint16_t Begin);
@@ -379,16 +380,14 @@ bool HexagonBitSimplify::getSubregMask(c
return true;
}
- assert(RR.Sub == Hexagon::subreg_loreg || RR.Sub == Hexagon::subreg_hireg);
- if (RR.Sub == Hexagon::subreg_loreg)
- Begin = 0;
+ Begin = 0;
switch (RC->getID()) {
case Hexagon::DoubleRegsRegClassID:
case Hexagon::VecDblRegsRegClassID:
case Hexagon::VecDblRegs128BRegClassID:
Width = RC->getSize()*8 / 2;
- if (RR.Sub == Hexagon::subreg_hireg)
+ if (RR.Sub == Hexagon::isub_hi || RR.Sub == Hexagon::vsub_hi)
Begin = Width;
break;
default:
@@ -401,16 +400,22 @@ bool HexagonBitSimplify::getSubregMask(c
// For a REG_SEQUENCE, set SL to the low subregister and SH to the high
// subregister.
bool HexagonBitSimplify::parseRegSequence(const MachineInstr &I,
- BitTracker::RegisterRef &SL, BitTracker::RegisterRef &SH) {
+ BitTracker::RegisterRef &SL, BitTracker::RegisterRef &SH,
+ const MachineRegisterInfo &MRI) {
assert(I.getOpcode() == TargetOpcode::REG_SEQUENCE);
unsigned Sub1 = I.getOperand(2).getImm(), Sub2 = I.getOperand(4).getImm();
- assert(Sub1 != Sub2);
- if (Sub1 == Hexagon::subreg_loreg && Sub2 == Hexagon::subreg_hireg) {
+ auto *DstRC = MRI.getRegClass(I.getOperand(0).getReg());
+ auto &HRI = static_cast<const HexagonRegisterInfo&>(
+ *MRI.getTargetRegisterInfo());
+ unsigned SubLo = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_lo);
+ unsigned SubHi = HRI.getHexagonSubRegIndex(DstRC, Hexagon::ps_sub_hi);
+ assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo));
+ if (Sub1 == SubLo && Sub2 == SubHi) {
SL = I.getOperand(1);
SH = I.getOperand(3);
return true;
}
- if (Sub1 == Hexagon::subreg_hireg && Sub2 == Hexagon::subreg_loreg) {
+ if (Sub1 == SubHi && Sub2 == SubLo) {
SH = I.getOperand(1);
SL = I.getOperand(3);
return true;
@@ -858,7 +863,7 @@ bool HexagonBitSimplify::getUsedBits(uns
// Calculate the register class that matches Reg:Sub. For example, if
-// vreg1 is a double register, then vreg1:subreg_hireg would match "int"
+// vreg1 is a double register, then vreg1:isub_hi would match the "int"
// register class.
const TargetRegisterClass *HexagonBitSimplify::getFinalVRegClass(
const BitTracker::RegisterRef &RR, MachineRegisterInfo &MRI) {
@@ -867,20 +872,23 @@ const TargetRegisterClass *HexagonBitSim
auto *RC = MRI.getRegClass(RR.Reg);
if (RR.Sub == 0)
return RC;
+ auto &HRI = static_cast<const HexagonRegisterInfo&>(
+ *MRI.getTargetRegisterInfo());
- auto VerifySR = [] (unsigned Sub) -> void {
- assert(Sub == Hexagon::subreg_hireg || Sub == Hexagon::subreg_loreg);
+ auto VerifySR = [&HRI] (const TargetRegisterClass *RC, unsigned Sub) -> void {
+ assert(Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo) ||
+ Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi));
};
switch (RC->getID()) {
case Hexagon::DoubleRegsRegClassID:
- VerifySR(RR.Sub);
+ VerifySR(RC, RR.Sub);
return &Hexagon::IntRegsRegClass;
case Hexagon::VecDblRegsRegClassID:
- VerifySR(RR.Sub);
+ VerifySR(RC, RR.Sub);
return &Hexagon::VectorRegsRegClass;
case Hexagon::VecDblRegs128BRegClassID:
- VerifySR(RR.Sub);
+ VerifySR(RC, RR.Sub);
return &Hexagon::VectorRegs128BRegClass;
}
return nullptr;
@@ -1212,11 +1220,11 @@ bool RedundantInstrElimination::computeU
// holds the bits for the entire register. To keep track of that, the
// argument Begin indicates where in Bits is the lowest-significant bit
// of the register used in operand OpN. For example, in instruction:
-// vreg1 = S2_lsr_i_r vreg2:subreg_hireg, 10
+// vreg1 = S2_lsr_i_r vreg2:isub_hi, 10
// the operand 1 is a 32-bit register, which happens to be a subregister
// of the 64-bit register vreg2, and that subregister starts at position 32.
// In this case Begin=32, since Bits[32] would be the lowest-significant bit
-// of vreg2:subreg_hireg.
+// of vreg2:isub_hi.
bool RedundantInstrElimination::computeUsedBits(const MachineInstr &MI,
unsigned OpN, BitVector &Bits, uint16_t Begin) {
unsigned Opc = MI.getOpcode();
@@ -1479,14 +1487,15 @@ namespace {
class CopyGeneration : public Transformation {
public:
CopyGeneration(BitTracker &bt, const HexagonInstrInfo &hii,
- MachineRegisterInfo &mri)
- : Transformation(true), HII(hii), MRI(mri), BT(bt) {}
+ const HexagonRegisterInfo &hri, MachineRegisterInfo &mri)
+ : Transformation(true), HII(hii), HRI(hri), MRI(mri), BT(bt) {}
bool processBlock(MachineBasicBlock &B, const RegisterSet &AVs) override;
private:
bool findMatch(const BitTracker::RegisterRef &Inp,
BitTracker::RegisterRef &Out, const RegisterSet &AVs);
const HexagonInstrInfo &HII;
+ const HexagonRegisterInfo &HRI;
MachineRegisterInfo &MRI;
BitTracker &BT;
RegisterSet Forbidden;
@@ -1495,12 +1504,13 @@ namespace {
class CopyPropagation : public Transformation {
public:
CopyPropagation(const HexagonRegisterInfo &hri, MachineRegisterInfo &mri)
- : Transformation(false), MRI(mri) {}
+ : Transformation(false), HRI(hri), MRI(mri) {}
bool processBlock(MachineBasicBlock &B, const RegisterSet &AVs) override;
static bool isCopyReg(unsigned Opc, bool NoConv);
private:
bool propagateRegCopy(MachineInstr &MI);
+ const HexagonRegisterInfo &HRI;
MachineRegisterInfo &MRI;
};
@@ -1544,9 +1554,9 @@ bool CopyGeneration::findMatch(const Bit
continue;
if (HBS::isEqual(InpRC, B, RC, 0, W))
- Out.Sub = Hexagon::subreg_loreg;
+ Out.Sub = Hexagon::isub_lo;
else if (HBS::isEqual(InpRC, B, RC, W, W))
- Out.Sub = Hexagon::subreg_hireg;
+ Out.Sub = Hexagon::isub_hi;
else
continue;
Out.Reg = R;
@@ -1597,17 +1607,19 @@ bool CopyGeneration::processBlock(Machin
FRC == &Hexagon::VecDblRegsRegClass ||
FRC == &Hexagon::VecDblRegs128BRegClass) {
// Try to generate REG_SEQUENCE.
- BitTracker::RegisterRef TL = { R, Hexagon::subreg_loreg };
- BitTracker::RegisterRef TH = { R, Hexagon::subreg_hireg };
+ unsigned SubLo = HRI.getHexagonSubRegIndex(FRC, Hexagon::ps_sub_lo);
+ unsigned SubHi = HRI.getHexagonSubRegIndex(FRC, Hexagon::ps_sub_hi);
+ BitTracker::RegisterRef TL = { R, SubLo };
+ BitTracker::RegisterRef TH = { R, SubHi };
BitTracker::RegisterRef ML, MH;
if (findMatch(TL, ML, AVB) && findMatch(TH, MH, AVB)) {
auto *FRC = HBS::getFinalVRegClass(R, MRI);
unsigned NewR = MRI.createVirtualRegister(FRC);
BuildMI(B, At, DL, HII.get(TargetOpcode::REG_SEQUENCE), NewR)
.addReg(ML.Reg, 0, ML.Sub)
- .addImm(Hexagon::subreg_loreg)
+ .addImm(SubLo)
.addReg(MH.Reg, 0, MH.Sub)
- .addImm(Hexagon::subreg_hireg);
+ .addImm(SubHi);
BT.put(BitTracker::RegisterRef(NewR), BT.get(R));
HBS::replaceReg(R, NewR, MRI);
Forbidden.insert(R);
@@ -1661,29 +1673,31 @@ bool CopyPropagation::propagateRegCopy(M
}
case TargetOpcode::REG_SEQUENCE: {
BitTracker::RegisterRef SL, SH;
- if (HBS::parseRegSequence(MI, SL, SH)) {
- Changed = HBS::replaceSubWithSub(RD.Reg, Hexagon::subreg_loreg,
- SL.Reg, SL.Sub, MRI);
- Changed |= HBS::replaceSubWithSub(RD.Reg, Hexagon::subreg_hireg,
- SH.Reg, SH.Sub, MRI);
+ if (HBS::parseRegSequence(MI, SL, SH, MRI)) {
+ const TargetRegisterClass *RC = MRI.getRegClass(RD.Reg);
+ unsigned SubLo = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo);
+ unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi);
+ Changed = HBS::replaceSubWithSub(RD.Reg, SubLo, SL.Reg, SL.Sub, MRI);
+ Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, SH.Reg, SH.Sub, MRI);
}
break;
}
case Hexagon::A2_combinew:
case Hexagon::V6_vcombine:
case Hexagon::V6_vcombine_128B: {
+ const TargetRegisterClass *RC = MRI.getRegClass(RD.Reg);
+ unsigned SubLo = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo);
+ unsigned SubHi = HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi);
BitTracker::RegisterRef RH = MI.getOperand(1), RL = MI.getOperand(2);
- Changed = HBS::replaceSubWithSub(RD.Reg, Hexagon::subreg_loreg,
- RL.Reg, RL.Sub, MRI);
- Changed |= HBS::replaceSubWithSub(RD.Reg, Hexagon::subreg_hireg,
- RH.Reg, RH.Sub, MRI);
+ Changed = HBS::replaceSubWithSub(RD.Reg, SubLo, RL.Reg, RL.Sub, MRI);
+ Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, RH.Reg, RH.Sub, MRI);
break;
}
case Hexagon::A4_combineir:
case Hexagon::A4_combineri: {
unsigned SrcX = (Opc == Hexagon::A4_combineir) ? 2 : 1;
- unsigned Sub = (Opc == Hexagon::A4_combineir) ? Hexagon::subreg_loreg
- : Hexagon::subreg_hireg;
+ unsigned Sub = (Opc == Hexagon::A4_combineir) ? Hexagon::isub_lo
+ : Hexagon::isub_hi;
BitTracker::RegisterRef RS = MI.getOperand(SrcX);
Changed = HBS::replaceSubWithSub(RD.Reg, Sub, RS.Reg, RS.Sub, MRI);
break;
@@ -1811,19 +1825,19 @@ bool BitSimplification::matchHalf(unsign
unsigned Sub = 0;
switch (Pos) {
case 0:
- Sub = Hexagon::subreg_loreg;
+ Sub = Hexagon::isub_lo;
Low = true;
break;
case 16:
- Sub = Hexagon::subreg_loreg;
+ Sub = Hexagon::isub_lo;
Low = false;
break;
case 32:
- Sub = Hexagon::subreg_hireg;
+ Sub = Hexagon::isub_hi;
Low = true;
break;
case 48:
- Sub = Hexagon::subreg_hireg;
+ Sub = Hexagon::isub_hi;
Low = false;
break;
default:
@@ -2174,10 +2188,10 @@ bool BitSimplification::simplifyTstbit(M
BitTracker::RegisterRef RR(V.RefI.Reg, 0);
if (TC == &Hexagon::DoubleRegsRegClass) {
P = V.RefI.Pos;
- RR.Sub = Hexagon::subreg_loreg;
+ RR.Sub = Hexagon::isub_lo;
if (P >= 32) {
P -= 32;
- RR.Sub = Hexagon::subreg_hireg;
+ RR.Sub = Hexagon::isub_hi;
}
} else if (TC == &Hexagon::IntRegsRegClass) {
P = V.RefI.Pos;
@@ -2296,7 +2310,7 @@ bool HexagonBitSimplify::runOnMachineFun
}
RegisterSet ACG; // Available registers for CG.
- CopyGeneration CopyG(BT, HII, MRI);
+ CopyGeneration CopyG(BT, HII, HRI, MRI);
Changed |= visitBlock(Entry, CopyG, ACG);
RegisterSet ACP; // Available registers for CP.
Modified: llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp?rev=286377&r1=286376&r2=286377&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp Wed Nov 9 10:19:08 2016
@@ -84,12 +84,14 @@ BT::BitMask HexagonEvaluator::mask(unsig
const TargetRegisterClass *RC = MRI.getRegClass(Reg);
unsigned ID = RC->getID();
uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub));
+ auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI);
+ bool IsSubLo = (Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo));
switch (ID) {
case DoubleRegsRegClassID:
case VecDblRegsRegClassID:
case VecDblRegs128BRegClassID:
- return (Sub == subreg_loreg) ? BT::BitMask(0, RW-1)
- : BT::BitMask(RW, 2*RW-1);
+ return IsSubLo ? BT::BitMask(0, RW-1)
+ : BT::BitMask(RW, 2*RW-1);
default:
break;
}
@@ -895,7 +897,7 @@ bool HexagonEvaluator::evaluate(const Ma
const CellMapType &Inputs,
BranchTargetList &Targets,
bool &FallsThru) const {
- // We need to evaluate one branch at a time. TII::AnalyzeBranch checks
+ // We need to evaluate one branch at a time. TII::analyzeBranch checks
// all the branches in a basic block at once, so we cannot use it.
unsigned Opc = BI.getOpcode();
bool SimpleBranch = false;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp?rev=286377&r1=286376&r2=286377&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp Wed Nov 9 10:19:08 2016
@@ -1946,12 +1946,15 @@ bool HexagonConstEvaluator::evaluate(con
if (MI.isRegSequence()) {
unsigned Sub1 = MI.getOperand(2).getImm();
unsigned Sub2 = MI.getOperand(4).getImm();
- if (Sub1 != Hexagon::subreg_loreg && Sub1 != Hexagon::subreg_hireg)
+ const TargetRegisterClass *DefRC = MRI->getRegClass(DefR.Reg);
+ unsigned SubLo = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_lo);
+ unsigned SubHi = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_hi);
+ if (Sub1 != SubLo && Sub1 != SubHi)
return false;
- if (Sub2 != Hexagon::subreg_loreg && Sub2 != Hexagon::subreg_hireg)
+ if (Sub2 != SubLo && Sub2 != SubHi)
return false;
assert(Sub1 != Sub2);
- bool LoIs1 = (Sub1 == Hexagon::subreg_loreg);
+ bool LoIs1 = (Sub1 == SubLo);
const MachineOperand &OpLo = LoIs1 ? MI.getOperand(1) : MI.getOperand(3);
const MachineOperand &OpHi = LoIs1 ? MI.getOperand(3) : MI.getOperand(1);
LatticeCell RC;
@@ -2196,11 +2199,10 @@ bool HexagonConstEvaluator::evaluate(con
Result = Input;
return true;
}
- // Predicate registers do not have subregisters.
const TargetRegisterClass *RC = MRI->getRegClass(R.Reg);
- if (RC == &Hexagon::PredRegsRegClass)
+ if (RC != &Hexagon::DoubleRegsRegClass)
return false;
- if (R.SubReg != Hexagon::subreg_loreg && R.SubReg != Hexagon::subreg_hireg)
+ if (R.SubReg != Hexagon::isub_lo && R.SubReg != Hexagon::isub_hi)
return false;
assert(!Input.isTop());
@@ -2215,7 +2217,7 @@ bool HexagonConstEvaluator::evaluate(con
Result.add(Ns);
return true;
}
- if (R.SubReg == Hexagon::subreg_hireg) {
+ if (R.SubReg == Hexagon::isub_hi) {
uint32_t Ns = (Ps & P::SignProperties);
Result.add(Ns);
return true;
@@ -2233,7 +2235,7 @@ bool HexagonConstEvaluator::evaluate(con
if (!A.isIntN(64))
return false;
uint64_t U = A.getZExtValue();
- if (R.SubReg == Hexagon::subreg_hireg)
+ if (R.SubReg == Hexagon::isub_hi)
U >>= 32;
U &= 0xFFFFFFFFULL;
uint32_t U32 = Lo_32(U);
Modified: llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp?rev=286377&r1=286376&r2=286377&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp Wed Nov 9 10:19:08 2016
@@ -580,23 +580,24 @@ void HexagonCopyToCombine::combine(Machi
unsigned I2DestReg = I2.getOperand(0).getReg();
bool IsI1Loreg = (I2DestReg - I1DestReg) == 1;
unsigned LoRegDef = IsI1Loreg ? I1DestReg : I2DestReg;
+ unsigned SubLo;
const TargetRegisterClass *SuperRC = nullptr;
if (Hexagon::IntRegsRegClass.contains(LoRegDef)) {
SuperRC = &Hexagon::DoubleRegsRegClass;
+ SubLo = Hexagon::isub_lo;
} else if (Hexagon::VectorRegsRegClass.contains(LoRegDef)) {
assert(ST->useHVXOps());
if (ST->useHVXSglOps())
SuperRC = &Hexagon::VecDblRegsRegClass;
else
SuperRC = &Hexagon::VecDblRegs128BRegClass;
+ SubLo = Hexagon::vsub_lo;
}
// Get the double word register.
- unsigned DoubleRegDest =
- TRI->getMatchingSuperReg(LoRegDef, Hexagon::subreg_loreg, SuperRC);
+ unsigned DoubleRegDest = TRI->getMatchingSuperReg(LoRegDef, SubLo, SuperRC);
assert(DoubleRegDest != 0 && "Expect a valid register");
-
// Setup source operands.
MachineOperand &LoOperand = IsI1Loreg ? I1.getOperand(1) : I2.getOperand(1);
MachineOperand &HiOperand = IsI1Loreg ? I2.getOperand(1) : I1.getOperand(1);
Modified: llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp?rev=286377&r1=286376&r2=286377&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp Wed Nov 9 10:19:08 2016
@@ -236,9 +236,11 @@ INITIALIZE_PASS_END(HexagonExpandCondset
unsigned HexagonExpandCondsets::getMaskForSub(unsigned Sub) {
switch (Sub) {
- case Hexagon::subreg_loreg:
+ case Hexagon::isub_lo:
+ case Hexagon::vsub_lo:
return Sub_Low;
- case Hexagon::subreg_hireg:
+ case Hexagon::isub_hi:
+ case Hexagon::vsub_hi:
return Sub_High;
case Hexagon::NoSubRegister:
return Sub_None;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp?rev=286377&r1=286376&r2=286377&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp Wed Nov 9 10:19:08 2016
@@ -876,8 +876,8 @@ void HexagonFrameLowering::insertCFIInst
// understand paired registers for cfi_offset.
// Eg .cfi_offset r1:0, -64
- unsigned HiReg = HRI.getSubReg(Reg, Hexagon::subreg_hireg);
- unsigned LoReg = HRI.getSubReg(Reg, Hexagon::subreg_loreg);
+ unsigned HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi);
+ unsigned LoReg = HRI.getSubReg(Reg, Hexagon::isub_lo);
unsigned HiDwarfReg = HRI.getDwarfRegNum(HiReg, true);
unsigned LoDwarfReg = HRI.getDwarfRegNum(LoReg, true);
auto OffHi = MCCFIInstruction::createOffset(FrameLabel, HiDwarfReg,
@@ -1639,8 +1639,8 @@ bool HexagonFrameLowering::expandStoreVe
DebugLoc DL = MI->getDebugLoc();
unsigned SrcR = MI->getOperand(2).getReg();
- unsigned SrcLo = HRI.getSubReg(SrcR, Hexagon::subreg_loreg);
- unsigned SrcHi = HRI.getSubReg(SrcR, Hexagon::subreg_hireg);
+ unsigned SrcLo = HRI.getSubReg(SrcR, Hexagon::vsub_lo);
+ unsigned SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi);
bool IsKill = MI->getOperand(2).isKill();
int FI = MI->getOperand(0).getIndex();
@@ -1697,8 +1697,8 @@ bool HexagonFrameLowering::expandLoadVec
DebugLoc DL = MI->getDebugLoc();
unsigned DstR = MI->getOperand(0).getReg();
- unsigned DstHi = HRI.getSubReg(DstR, Hexagon::subreg_hireg);
- unsigned DstLo = HRI.getSubReg(DstR, Hexagon::subreg_loreg);
+ unsigned DstHi = HRI.getSubReg(DstR, Hexagon::vsub_hi);
+ unsigned DstLo = HRI.getSubReg(DstR, Hexagon::vsub_lo);
int FI = MI->getOperand(1).getIndex();
bool Is128B = HST.useHVXDblOps();
Modified: llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp?rev=286377&r1=286376&r2=286377&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp Wed Nov 9 10:19:08 2016
@@ -1387,9 +1387,9 @@ bool HexagonGenInsert::generateInserts()
unsigned Wdh = IF.Wdh, Off = IF.Off;
unsigned InsS = 0;
if (R32 && MRI->getRegClass(IF.InsR) == &Hexagon::DoubleRegsRegClass) {
- InsS = Hexagon::subreg_loreg;
+ InsS = Hexagon::isub_lo;
if (Off >= 32) {
- InsS = Hexagon::subreg_hireg;
+ InsS = Hexagon::isub_hi;
Off -= 32;
}
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp?rev=286377&r1=286376&r2=286377&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp Wed Nov 9 10:19:08 2016
@@ -356,7 +356,7 @@ bool HexagonGenPredicate::convertToPredF
if (!MO.isReg() || !MO.isUse())
continue;
Register Reg(MO);
- if (Reg.S && Reg.S != Hexagon::subreg_loreg)
+ if (Reg.S && Reg.S != Hexagon::isub_lo)
return false;
if (!PredGPRs.count(Reg))
return false;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp?rev=286377&r1=286376&r2=286377&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp Wed Nov 9 10:19:08 2016
@@ -1501,9 +1501,9 @@ bool HexagonHardwareLoops::checkForImmed
return false;
unsigned Sub2 = DI->getOperand(2).getImm();
unsigned Sub4 = DI->getOperand(4).getImm();
- if (Sub2 == Hexagon::subreg_loreg && Sub4 == Hexagon::subreg_hireg)
+ if (Sub2 == Hexagon::isub_lo && Sub4 == Hexagon::isub_hi)
TV = V1 | (V3 << 32);
- else if (Sub2 == Hexagon::subreg_hireg && Sub4 == Hexagon::subreg_loreg)
+ else if (Sub2 == Hexagon::isub_hi && Sub4 == Hexagon::isub_lo)
TV = V3 | (V1 << 32);
else
llvm_unreachable("Unexpected form of REG_SEQUENCE");
@@ -1517,10 +1517,10 @@ bool HexagonHardwareLoops::checkForImmed
// By now, we should have successfuly obtained the immediate value defining
// the register referenced in MO. Handle a potential use of a subregister.
switch (MO.getSubReg()) {
- case Hexagon::subreg_loreg:
+ case Hexagon::isub_lo:
Val = TV & 0xFFFFFFFFULL;
break;
- case Hexagon::subreg_hireg:
+ case Hexagon::isub_hi:
Val = (TV >> 32) & 0xFFFFFFFFULL;
break;
default:
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp?rev=286377&r1=286376&r2=286377&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp Wed Nov 9 10:19:08 2016
@@ -542,7 +542,7 @@ void HexagonDAGToDAGISel::SelectIndexedS
if (ST->isTruncatingStore() && ValueVT.getSizeInBits() == 64) {
assert(StoredVT.getSizeInBits() < 64 && "Not a truncating store");
- Value = CurDAG->getTargetExtractSubreg(Hexagon::subreg_loreg,
+ Value = CurDAG->getTargetExtractSubreg(Hexagon::isub_lo,
dl, MVT::i32, Value);
}
@@ -764,8 +764,7 @@ void HexagonDAGToDAGISel::SelectZeroExte
if (ExVT.getSizeInBits() == 32) {
SDNode *And = CurDAG->getMachineNode(Hexagon::A2_andp, dl, MVT::i64,
SDValue(Mask,0), SDValue(OnesReg,0));
- SDValue SubR = CurDAG->getTargetConstant(Hexagon::subreg_loreg, dl,
- MVT::i32);
+ SDValue SubR = CurDAG->getTargetConstant(Hexagon::isub_lo, dl, MVT::i32);
ReplaceNode(N, CurDAG->getMachineNode(Hexagon::EXTRACT_SUBREG, dl, ExVT,
SDValue(And, 0), SubR));
return;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=286377&r1=286376&r2=286377&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Wed Nov 9 10:19:08 2016
@@ -2558,7 +2558,7 @@ HexagonTargetLowering::LowerBUILD_VECTOR
SDValue pack = DAG.getNode(HexagonISD::PACKHL, dl, MVT::v4i16,
BVN->getOperand(1), BVN->getOperand(0));
- return DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl, MVT::v2i16,
+ return DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::v2i16,
pack);
}
}
@@ -2730,14 +2730,12 @@ HexagonTargetLowering::LowerEXTRACT_SUBV
// These two will get lowered to an appropriate EXTRACT_SUBREG in ISel.
if (Val == 0) {
SDValue Vec = Op.getOperand(0);
- unsigned Subreg = Hexagon::subreg_loreg;
- return DAG.getTargetExtractSubreg(Subreg, dl, ResVT, Vec);
+ return DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, ResVT, Vec);
}
if (ResVT.getVectorNumElements() == Val) {
SDValue Vec = Op.getOperand(0);
- unsigned Subreg = Hexagon::subreg_hireg;
- return DAG.getTargetExtractSubreg(Subreg, dl, ResVT, Vec);
+ return DAG.getTargetExtractSubreg(Hexagon::vsub_hi, dl, ResVT, Vec);
}
return SDValue();
@@ -2778,16 +2776,16 @@ HexagonTargetLowering::LowerEXTRACT_VECT
if (W == 32) {
// Translate this node into EXTRACT_SUBREG.
- unsigned Subreg = (X == 0) ? Hexagon::subreg_loreg : 0;
+ unsigned Subreg = (X == 0) ? Hexagon::isub_lo : 0;
if (X == 0)
- Subreg = Hexagon::subreg_loreg;
+ Subreg = Hexagon::isub_lo;
else if (SVT == MVT::v2i32 && X == 1)
- Subreg = Hexagon::subreg_hireg;
+ Subreg = Hexagon::isub_hi;
else if (SVT == MVT::v4i16 && X == 2)
- Subreg = Hexagon::subreg_hireg;
+ Subreg = Hexagon::isub_hi;
else if (SVT == MVT::v8i8 && X == 4)
- Subreg = Hexagon::subreg_hireg;
+ Subreg = Hexagon::isub_hi;
else
llvm_unreachable("Bad offset");
N = DAG.getTargetExtractSubreg(Subreg, dl, MVT::i32, Vec);
@@ -2797,7 +2795,7 @@ HexagonTargetLowering::LowerEXTRACT_VECT
} else if (SVT.getSizeInBits() == 64) {
N = DAG.getNode(HexagonISD::EXTRACTU, dl, MVT::i64, Ops);
if (VT.getSizeInBits() == 32)
- N = DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl, MVT::i32, N);
+ N = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, N);
} else
return SDValue();
@@ -2819,7 +2817,7 @@ HexagonTargetLowering::LowerEXTRACT_VECT
} else {
N = DAG.getNode(HexagonISD::EXTRACTURP, dl, MVT::i64, Ops);
if (VT.getSizeInBits() == 32)
- N = DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl, MVT::i32, N);
+ N = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, N);
}
return DAG.getNode(ISD::BITCAST, dl, VT, N);
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=286377&r1=286376&r2=286377&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Wed Nov 9 10:19:08 2016
@@ -116,8 +116,8 @@ static bool isIntRegForSubInst(unsigned
static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) {
- return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::subreg_loreg)) &&
- isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::subreg_hireg));
+ return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) &&
+ isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi));
}
@@ -821,9 +821,11 @@ void HexagonInstrInfo::copyPhysReg(Machi
return;
}
if (Hexagon::VecDblRegsRegClass.contains(SrcReg, DestReg)) {
+ unsigned LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
+ unsigned HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg)
- .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_hireg), KillFlag)
- .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_loreg), KillFlag);
+ .addReg(HiSrc, KillFlag)
+ .addReg(LoSrc, KillFlag);
return;
}
if (Hexagon::VecPredRegsRegClass.contains(SrcReg, DestReg)) {
@@ -843,12 +845,14 @@ void HexagonInstrInfo::copyPhysReg(Machi
return;
}
if (Hexagon::VecPredRegs128BRegClass.contains(SrcReg, DestReg)) {
- unsigned DstHi = HRI.getSubReg(DestReg, Hexagon::subreg_hireg);
- BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DstHi)
- .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_hireg), KillFlag);
- unsigned DstLo = HRI.getSubReg(DestReg, Hexagon::subreg_loreg);
- BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DstLo)
- .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_loreg), KillFlag);
+ unsigned HiDst = HRI.getSubReg(DestReg, Hexagon::vsub_hi);
+ unsigned LoDst = HRI.getSubReg(DestReg, Hexagon::vsub_lo);
+ unsigned HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
+ unsigned LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
+ BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), HiDst)
+ .addReg(HiSrc, KillFlag);
+ BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), LoDst)
+ .addReg(LoSrc, KillFlag);
return;
}
@@ -1031,8 +1035,8 @@ bool HexagonInstrInfo::expandPostRAPseud
unsigned DstReg = MI.getOperand(0).getReg();
unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg)
- .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_hireg), Kill)
- .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_loreg), Kill);
+ .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi), Kill)
+ .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo), Kill);
MBB.erase(MI);
return true;
}
@@ -1040,7 +1044,7 @@ bool HexagonInstrInfo::expandPostRAPseud
case Hexagon::V6_lo: {
unsigned SrcReg = MI.getOperand(1).getReg();
unsigned DstReg = MI.getOperand(0).getReg();
- unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::subreg_loreg);
+ unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
copyPhysReg(MBB, MI, DL, DstReg, SrcSubLo, MI.getOperand(1).isKill());
MBB.erase(MI);
MRI.clearKillFlags(SrcSubLo);
@@ -1050,7 +1054,7 @@ bool HexagonInstrInfo::expandPostRAPseud
case Hexagon::V6_hi: {
unsigned SrcReg = MI.getOperand(1).getReg();
unsigned DstReg = MI.getOperand(0).getReg();
- unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::subreg_hireg);
+ unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
copyPhysReg(MBB, MI, DL, DstReg, SrcSubHi, MI.getOperand(1).isKill());
MBB.erase(MI);
MRI.clearKillFlags(SrcSubHi);
@@ -1065,8 +1069,8 @@ bool HexagonInstrInfo::expandPostRAPseud
bool Aligned = (Opc == Hexagon::PS_vstorerw_ai ||
Opc == Hexagon::PS_vstorerw_ai_128B);
unsigned SrcReg = MI.getOperand(2).getReg();
- unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::subreg_hireg);
- unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::subreg_loreg);
+ unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
+ unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
unsigned NewOpc;
if (Aligned)
NewOpc = Is128B ? Hexagon::V6_vS32b_ai_128B
@@ -1112,12 +1116,12 @@ bool HexagonInstrInfo::expandPostRAPseud
unsigned Offset = Is128B ? VecOffset << 7 : VecOffset << 6;
MachineInstr *MI1New =
BuildMI(MBB, MI, DL, get(NewOpc),
- HRI.getSubReg(DstReg, Hexagon::subreg_loreg))
+ HRI.getSubReg(DstReg, Hexagon::vsub_lo))
.addOperand(MI.getOperand(1))
.addImm(MI.getOperand(2).getImm());
MI1New->getOperand(1).setIsKill(false);
BuildMI(MBB, MI, DL, get(NewOpc),
- HRI.getSubReg(DstReg, Hexagon::subreg_hireg))
+ HRI.getSubReg(DstReg, Hexagon::vsub_hi))
.addOperand(MI.getOperand(1))
// The Vectors are indexed in multiples of vector size.
.addImm(MI.getOperand(2).getImm() + Offset)
@@ -1146,16 +1150,16 @@ bool HexagonInstrInfo::expandPostRAPseud
unsigned DstReg = MI.getOperand(0).getReg();
unsigned Src1Reg = MI.getOperand(1).getReg();
unsigned Src2Reg = MI.getOperand(2).getReg();
- unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
- unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
- unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
- unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
+ unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
+ unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
+ unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
+ unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
- HRI.getSubReg(DstReg, Hexagon::subreg_hireg))
+ HRI.getSubReg(DstReg, Hexagon::isub_hi))
.addReg(Src1SubHi)
.addReg(Src2SubHi);
BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
- HRI.getSubReg(DstReg, Hexagon::subreg_loreg))
+ HRI.getSubReg(DstReg, Hexagon::isub_lo))
.addReg(Src1SubLo)
.addReg(Src2SubLo);
MBB.erase(MI);
@@ -1171,19 +1175,19 @@ bool HexagonInstrInfo::expandPostRAPseud
unsigned Src1Reg = MI.getOperand(1).getReg();
unsigned Src2Reg = MI.getOperand(2).getReg();
unsigned Src3Reg = MI.getOperand(3).getReg();
- unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
- unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
- unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
- unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
- unsigned Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::subreg_hireg);
- unsigned Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::subreg_loreg);
+ unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
+ unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
+ unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
+ unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
+ unsigned Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
+ unsigned Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
- HRI.getSubReg(DstReg, Hexagon::subreg_hireg))
+ HRI.getSubReg(DstReg, Hexagon::isub_hi))
.addReg(Src1SubHi)
.addReg(Src2SubHi)
.addReg(Src3SubHi);
BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
- HRI.getSubReg(DstReg, Hexagon::subreg_loreg))
+ HRI.getSubReg(DstReg, Hexagon::isub_lo))
.addReg(Src1SubLo)
.addReg(Src2SubLo)
.addReg(Src3SubLo);
@@ -1260,8 +1264,8 @@ bool HexagonInstrInfo::expandPostRAPseud
bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
if (Op0.getReg() != Op2.getReg()) {
- unsigned SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::subreg_loreg);
- unsigned SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::subreg_hireg);
+ unsigned SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
+ unsigned SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine))
.addOperand(Op0)
.addOperand(Op1)
@@ -1272,8 +1276,8 @@ bool HexagonInstrInfo::expandPostRAPseud
IsDestLive = true;
}
if (Op0.getReg() != Op3.getReg()) {
- unsigned SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::subreg_loreg);
- unsigned SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::subreg_hireg);
+ unsigned SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo);
+ unsigned SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine))
.addOperand(Op0)
.addOperand(Op1)
Modified: llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsDerived.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsDerived.td?rev=286377&r1=286376&r2=286377&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsDerived.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsDerived.td Wed Nov 9 10:19:08 2016
@@ -20,21 +20,21 @@ def : Pat <(mul DoubleRegs:$src1, Double
(EXTRACT_SUBREG
(i64
(M2_dpmpyuu_s0 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
- subreg_loreg)),
+ isub_lo)),
(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
- subreg_loreg)))),
- subreg_hireg)),
- (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
- (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))),
- (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)),
- (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg))),
+ isub_lo)))),
+ isub_hi)),
+ (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), isub_lo)),
+ (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), isub_hi))),
+ (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), isub_lo)),
+ (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), isub_hi))),
(i32
(EXTRACT_SUBREG
(i64
(M2_dpmpyuu_s0
- (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
+ (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), isub_lo)),
(i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
- subreg_loreg)))), subreg_loreg))))>;
+ isub_lo)))), isub_lo))))>;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsV60.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsV60.td?rev=286377&r1=286376&r2=286377&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsV60.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsV60.td Wed Nov 9 10:19:08 2016
@@ -14,21 +14,19 @@
let AddedComplexity = 100 in {
def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 VecDblRegs:$src1))),
- (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), subreg_loreg)) >,
+ (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), vsub_lo)) >,
Requires<[UseHVXSgl]>;
def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 VecDblRegs:$src1))),
- (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), subreg_hireg)) >,
+ (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), vsub_hi)) >,
Requires<[UseHVXSgl]>;
def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 VecDblRegs128B:$src1))),
- (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1),
- subreg_loreg)) >,
+ (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1), vsub_lo)) >,
Requires<[UseHVXDbl]>;
def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 VecDblRegs128B:$src1))),
- (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1),
- subreg_hireg)) >,
+ (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1), vsub_hi)) >,
Requires<[UseHVXDbl]>;
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td?rev=286377&r1=286376&r2=286377&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td Wed Nov 9 10:19:08 2016
@@ -11,10 +11,8 @@ def F64 : PatLeaf<(f64 DoubleRegs:$R)>;
// Pattern fragments to extract the low and high subregisters from a
// 64-bit value.
-def LoReg: OutPatFrag<(ops node:$Rs),
- (EXTRACT_SUBREG (i64 $Rs), subreg_loreg)>;
-def HiReg: OutPatFrag<(ops node:$Rs),
- (EXTRACT_SUBREG (i64 $Rs), subreg_hireg)>;
+def LoReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_lo)>;
+def HiReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_hi)>;
def orisadd: PatFrag<(ops node:$Addr, node:$off),
(or node:$Addr, node:$off), [{ return orIsAdd(N); }]>;
@@ -594,33 +592,33 @@ let AddedComplexity = 20 in { // Complex
let AddedComplexity = 20 in { // Complexity greater than and/or/xor
def: Pat<(and I64:$Rss, IsNPow2_64L:$V),
(REG_SEQUENCE DoubleRegs,
- (i32 (HiReg $Rss)), subreg_hireg,
- (S2_clrbit_i (LoReg $Rss), (LogN2_64 $V)), subreg_loreg)>;
+ (i32 (HiReg $Rss)), isub_hi,
+ (S2_clrbit_i (LoReg $Rss), (LogN2_64 $V)), isub_lo)>;
def: Pat<(and I64:$Rss, IsNPow2_64H:$V),
(REG_SEQUENCE DoubleRegs,
(S2_clrbit_i (HiReg $Rss), (UDEC32 (i32 (LogN2_64 $V)))),
- subreg_hireg,
- (i32 (LoReg $Rss)), subreg_loreg)>;
+ isub_hi,
+ (i32 (LoReg $Rss)), isub_lo)>;
def: Pat<(or I64:$Rss, IsPow2_64L:$V),
(REG_SEQUENCE DoubleRegs,
- (i32 (HiReg $Rss)), subreg_hireg,
- (S2_setbit_i (LoReg $Rss), (Log2_64 $V)), subreg_loreg)>;
+ (i32 (HiReg $Rss)), isub_hi,
+ (S2_setbit_i (LoReg $Rss), (Log2_64 $V)), isub_lo)>;
def: Pat<(or I64:$Rss, IsPow2_64H:$V),
(REG_SEQUENCE DoubleRegs,
(S2_setbit_i (HiReg $Rss), (UDEC32 (i32 (Log2_64 $V)))),
- subreg_hireg,
- (i32 (LoReg $Rss)), subreg_loreg)>;
+ isub_hi,
+ (i32 (LoReg $Rss)), isub_lo)>;
def: Pat<(xor I64:$Rss, IsPow2_64L:$V),
(REG_SEQUENCE DoubleRegs,
- (i32 (HiReg $Rss)), subreg_hireg,
- (S2_togglebit_i (LoReg $Rss), (Log2_64 $V)), subreg_loreg)>;
+ (i32 (HiReg $Rss)), isub_hi,
+ (S2_togglebit_i (LoReg $Rss), (Log2_64 $V)), isub_lo)>;
def: Pat<(xor I64:$Rss, IsPow2_64H:$V),
(REG_SEQUENCE DoubleRegs,
(S2_togglebit_i (HiReg $Rss), (UDEC32 (i32 (Log2_64 $V)))),
- subreg_hireg,
- (i32 (LoReg $Rss)), subreg_loreg)>;
+ isub_hi,
+ (i32 (LoReg $Rss)), isub_lo)>;
}
let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
@@ -2695,13 +2693,13 @@ def : Pat <(fneg F32:$src1),
def: Pat<(fabs F64:$Rs),
(REG_SEQUENCE DoubleRegs,
- (S2_clrbit_i (HiReg $Rs), 31), subreg_hireg,
- (i32 (LoReg $Rs)), subreg_loreg)>;
+ (S2_clrbit_i (HiReg $Rs), 31), isub_hi,
+ (i32 (LoReg $Rs)), isub_lo)>;
def: Pat<(fneg F64:$Rs),
(REG_SEQUENCE DoubleRegs,
- (S2_togglebit_i (HiReg $Rs), 31), subreg_hireg,
- (i32 (LoReg $Rs)), subreg_loreg)>;
+ (S2_togglebit_i (HiReg $Rs), 31), isub_hi,
+ (i32 (LoReg $Rs)), isub_lo)>;
def alignedload : PatFrag<(ops node:$addr), (load $addr), [{
return isAlignedMemNode(dyn_cast<MemSDNode>(N));
Modified: llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp?rev=286377&r1=286376&r2=286377&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonPeephole.cpp Wed Nov 9 10:19:08 2016
@@ -10,7 +10,7 @@
// Transform the following pattern
// %vreg170<def> = SXTW %vreg166
// ...
-// %vreg176<def> = COPY %vreg170:subreg_loreg
+// %vreg176<def> = COPY %vreg170:isub_lo
//
// Into
// %vreg176<def> = COPY vreg166
@@ -167,9 +167,9 @@ bool HexagonPeephole::runOnMachineFuncti
// Look for this sequence below
// %vregDoubleReg1 = LSRd_ri %vregDoubleReg0, 32
- // %vregIntReg = COPY %vregDoubleReg1:subreg_loreg.
+ // %vregIntReg = COPY %vregDoubleReg1:isub_lo.
// and convert into
- // %vregIntReg = COPY %vregDoubleReg0:subreg_hireg.
+ // %vregIntReg = COPY %vregDoubleReg0:isub_hi.
if (MI.getOpcode() == Hexagon::S2_lsr_i_p) {
assert(MI.getNumOperands() == 3);
MachineOperand &Dst = MI.getOperand(0);
@@ -180,7 +180,7 @@ bool HexagonPeephole::runOnMachineFuncti
unsigned DstReg = Dst.getReg();
unsigned SrcReg = Src1.getReg();
PeepholeDoubleRegsMap[DstReg] =
- std::make_pair(*&SrcReg, Hexagon::subreg_hireg);
+ std::make_pair(*&SrcReg, Hexagon::isub_hi);
}
// Look for P=NOT(P).
@@ -201,14 +201,14 @@ bool HexagonPeephole::runOnMachineFuncti
}
// Look for copy:
- // %vreg176<def> = COPY %vreg170:subreg_loreg
+ // %vreg176<def> = COPY %vreg170:isub_lo
if (!DisableOptSZExt && MI.isCopy()) {
assert(MI.getNumOperands() == 2);
MachineOperand &Dst = MI.getOperand(0);
MachineOperand &Src = MI.getOperand(1);
// Make sure we are copying the lower 32 bits.
- if (Src.getSubReg() != Hexagon::subreg_loreg)
+ if (Src.getSubReg() != Hexagon::isub_lo)
continue;
unsigned DstReg = Dst.getReg();
Modified: llvm/trunk/lib/Target/Hexagon/HexagonRDFOpt.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRDFOpt.cpp?rev=286377&r1=286376&r2=286377&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonRDFOpt.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonRDFOpt.cpp Wed Nov 9 10:19:08 2016
@@ -106,9 +106,9 @@ bool HexagonCP::interpretAsCopy(const Ma
const MachineOperand &HiOp = MI->getOperand(1);
const MachineOperand &LoOp = MI->getOperand(2);
assert(DstOp.getSubReg() == 0 && "Unexpected subregister");
- mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::subreg_hireg),
+ mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_hi),
DFG.makeRegRef(HiOp.getReg(), HiOp.getSubReg()));
- mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::subreg_loreg),
+ mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_lo),
DFG.makeRegRef(LoOp.getReg(), LoOp.getSubReg()));
return true;
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp?rev=286377&r1=286376&r2=286377&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp Wed Nov 9 10:19:08 2016
@@ -235,6 +235,28 @@ unsigned HexagonRegisterInfo::getStackRe
}
+unsigned HexagonRegisterInfo::getHexagonSubRegIndex(
+ const TargetRegisterClass *RC, unsigned GenIdx) const {
+ assert(GenIdx == Hexagon::ps_sub_lo || GenIdx == Hexagon::ps_sub_hi);
+
+ static const unsigned ISub[] = { Hexagon::isub_lo, Hexagon::isub_hi };
+ static const unsigned VSub[] = { Hexagon::vsub_lo, Hexagon::vsub_hi };
+
+ switch (RC->getID()) {
+ case Hexagon::CtrRegs64RegClassID:
+ case Hexagon::DoubleRegsRegClassID:
+ return ISub[GenIdx];
+ case Hexagon::VecDblRegsRegClassID:
+ case Hexagon::VecDblRegs128BRegClassID:
+ return VSub[GenIdx];
+ }
+
+ if (const TargetRegisterClass *SuperRC = *RC->getSuperClasses())
+ return getHexagonSubRegIndex(SuperRC, GenIdx);
+
+ llvm_unreachable("Invalid register class");
+}
+
bool HexagonRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF)
const {
return MF.getSubtarget<HexagonSubtarget>().getFrameLowering()->hasFP(MF);
Modified: llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.h?rev=286377&r1=286376&r2=286377&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.h Wed Nov 9 10:19:08 2016
@@ -22,6 +22,12 @@
#include "HexagonGenRegisterInfo.inc"
namespace llvm {
+
+namespace Hexagon {
+ // Generic (pseudo) subreg indices for use with getHexagonSubRegIndex.
+ enum { ps_sub_lo = 0, ps_sub_hi = 1 };
+}
+
class HexagonRegisterInfo : public HexagonGenRegisterInfo {
public:
HexagonRegisterInfo();
@@ -61,6 +67,9 @@ public:
unsigned getFrameRegister() const;
unsigned getStackRegister() const;
+ unsigned getHexagonSubRegIndex(const TargetRegisterClass *RC,
+ unsigned GenIdx) const;
+
const MCPhysReg *getCallerSavedRegs(const MachineFunction *MF,
const TargetRegisterClass *RC) const;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td?rev=286377&r1=286376&r2=286377&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td Wed Nov 9 10:19:08 2016
@@ -81,8 +81,10 @@ let Namespace = "Hexagon" in {
let Num = !cast<bits<5>>(num);
}
- def subreg_loreg : SubRegIndex<32>;
- def subreg_hireg : SubRegIndex<32, 32>;
+ def isub_lo : SubRegIndex<32>;
+ def isub_hi : SubRegIndex<32, 32>;
+ def vsub_lo : SubRegIndex<512>;
+ def vsub_hi : SubRegIndex<512, 512>;
def subreg_overflow : SubRegIndex<1, 0>;
// Integer registers.
@@ -95,7 +97,7 @@ let Namespace = "Hexagon" in {
def R31 : Ri<31, "r31", ["lr"]>, DwarfRegNum<[31]>;
// Aliases of the R* registers used to hold 64-bit int values (doubles).
- let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in {
+ let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in {
def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>;
def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>;
def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>;
@@ -150,7 +152,7 @@ let Namespace = "Hexagon" in {
// Define C8 separately and make it aliased with USR.
// The problem is that USR has subregisters (e.g. overflow). If USR was
// specified as a subregister of C9_8, it would imply that subreg_overflow
- // and subreg_loreg can be composed, which leads to all kinds of issues
+ // and isub_lo can be composed, which leads to all kinds of issues
// with lane masks.
def C8 : Rc<8, "c8", [], [USR]>, DwarfRegNum<[75]>;
def PC : Rc<9, "pc">, DwarfRegNum<[76]>;
@@ -163,7 +165,7 @@ let Namespace = "Hexagon" in {
}
// Control registers pairs.
- let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in {
+ let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in {
def C1_0 : Rcc<0, "c1:0", [SA0, LC0], ["lc0:sa0"]>, DwarfRegNum<[67]>;
def C3_2 : Rcc<2, "c3:2", [SA1, LC1], ["lc1:sa1"]>, DwarfRegNum<[69]>;
def C5_4 : Rcc<4, "c5:4", [P3_0, C5]>, DwarfRegNum<[71]>;
@@ -180,7 +182,7 @@ let Namespace = "Hexagon" in {
}
// Aliases of the V* registers used to hold double vec values.
- let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in {
+ let SubRegIndices = [vsub_lo, vsub_hi], CoveredBySubRegs = 1 in {
def W0 : Rd< 0, "v1:0", [V0, V1]>, DwarfRegNum<[99]>;
def W1 : Rd< 2, "v3:2", [V2, V3]>, DwarfRegNum<[101]>;
def W2 : Rd< 4, "v5:4", [V4, V5]>, DwarfRegNum<[103]>;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp?rev=286377&r1=286376&r2=286377&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp Wed Nov 9 10:19:08 2016
@@ -87,8 +87,8 @@ bool HexagonSplitConst32AndConst64::runO
unsigned DestReg = MI.getOperand(0).getReg();
int64_t ImmValue = MI.getOperand(1).getImm();
const DebugLoc &DL = MI.getDebugLoc();
- unsigned DestLo = TRI->getSubReg(DestReg, Hexagon::subreg_loreg);
- unsigned DestHi = TRI->getSubReg(DestReg, Hexagon::subreg_hireg);
+ unsigned DestLo = TRI->getSubReg(DestReg, Hexagon::isub_lo);
+ unsigned DestHi = TRI->getSubReg(DestReg, Hexagon::isub_hi);
int32_t LowWord = (ImmValue & 0xFFFFFFFF);
int32_t HighWord = (ImmValue >> 32) & 0xFFFFFFFF;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp?rev=286377&r1=286376&r2=286377&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp Wed Nov 9 10:19:08 2016
@@ -441,7 +441,7 @@ void HexagonSplitDoubleRegs::collectIndR
MachineBasicBlock *TmpLB = const_cast<MachineBasicBlock*>(LB);
SmallVector<MachineOperand,2> Cond;
bool BadLB = TII->analyzeBranch(*TmpLB, TB, FB, Cond, false);
- // Only analyzable conditional branches. HII::AnalyzeBranch will put
+ // Only analyzable conditional branches. HII::analyzeBranch will put
// the branch opcode as the first element of Cond, and the predicate
// operand as the second.
if (BadLB || Cond.size() != 2)
@@ -452,7 +452,7 @@ void HexagonSplitDoubleRegs::collectIndR
// Must go to the header.
if (TB != HB && FB != HB)
return;
- assert(Cond[1].isReg() && "Unexpected Cond vector from AnalyzeBranch");
+ assert(Cond[1].isReg() && "Unexpected Cond vector from analyzeBranch");
// Expect a predicate register.
unsigned PR = Cond[1].getReg();
assert(MRI->getRegClass(PR) == &Hexagon::PredRegsRegClass);
@@ -569,7 +569,7 @@ void HexagonSplitDoubleRegs::createHalfI
SR = SubR;
} else {
const UUPair &P = F->second;
- R = (SubR == Hexagon::subreg_loreg) ? P.first : P.second;
+ R = (SubR == Hexagon::isub_lo) ? P.first : P.second;
SR = 0;
}
}
@@ -763,8 +763,8 @@ void HexagonSplitDoubleRegs::splitShift(
unsigned RS = getRegState(Op1);
unsigned ShiftOpc = Left ? S2_asl_i_r
: (Signed ? S2_asr_i_r : S2_lsr_i_r);
- unsigned LoSR = subreg_loreg;
- unsigned HiSR = subreg_hireg;
+ unsigned LoSR = isub_lo;
+ unsigned HiSR = isub_hi;
if (S == 0) {
// No shift, subregister copy.
@@ -884,8 +884,8 @@ void HexagonSplitDoubleRegs::splitAslOr(
unsigned RS2 = getRegState(Op2);
const TargetRegisterClass *IntRC = &IntRegsRegClass;
- unsigned LoSR = subreg_loreg;
- unsigned HiSR = subreg_hireg;
+ unsigned LoSR = isub_lo;
+ unsigned HiSR = isub_hi;
// Op0 = S2_asl_i_p_or Op1, Op2, Op3
// means: Op0 = or (Op1, asl(Op2, Op3))
@@ -965,25 +965,25 @@ bool HexagonSplitDoubleRegs::splitInstr(
case TargetOpcode::COPY: {
unsigned DstR = MI->getOperand(0).getReg();
if (MRI->getRegClass(DstR) == DoubleRC) {
- createHalfInstr(Opc, MI, PairMap, subreg_loreg);
- createHalfInstr(Opc, MI, PairMap, subreg_hireg);
+ createHalfInstr(Opc, MI, PairMap, isub_lo);
+ createHalfInstr(Opc, MI, PairMap, isub_hi);
Split = true;
}
break;
}
case A2_andp:
- createHalfInstr(A2_and, MI, PairMap, subreg_loreg);
- createHalfInstr(A2_and, MI, PairMap, subreg_hireg);
+ createHalfInstr(A2_and, MI, PairMap, isub_lo);
+ createHalfInstr(A2_and, MI, PairMap, isub_hi);
Split = true;
break;
case A2_orp:
- createHalfInstr(A2_or, MI, PairMap, subreg_loreg);
- createHalfInstr(A2_or, MI, PairMap, subreg_hireg);
+ createHalfInstr(A2_or, MI, PairMap, isub_lo);
+ createHalfInstr(A2_or, MI, PairMap, isub_hi);
Split = true;
break;
case A2_xorp:
- createHalfInstr(A2_xor, MI, PairMap, subreg_loreg);
- createHalfInstr(A2_xor, MI, PairMap, subreg_hireg);
+ createHalfInstr(A2_xor, MI, PairMap, isub_lo);
+ createHalfInstr(A2_xor, MI, PairMap, isub_hi);
Split = true;
break;
@@ -1047,10 +1047,10 @@ void HexagonSplitDoubleRegs::replaceSubr
continue;
const UUPair &P = F->second;
switch (Op.getSubReg()) {
- case Hexagon::subreg_loreg:
+ case Hexagon::isub_lo:
Op.setReg(P.first);
break;
- case Hexagon::subreg_hireg:
+ case Hexagon::isub_hi:
Op.setReg(P.second);
break;
}
@@ -1079,9 +1079,9 @@ void HexagonSplitDoubleRegs::collapseReg
unsigned NewDR = MRI->createVirtualRegister(DoubleRC);
BuildMI(B, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), NewDR)
.addReg(Pr.first)
- .addImm(Hexagon::subreg_loreg)
+ .addImm(Hexagon::isub_lo)
.addReg(Pr.second)
- .addImm(Hexagon::subreg_hireg);
+ .addImm(Hexagon::isub_hi);
Op.setReg(NewDR);
}
}
Modified: llvm/trunk/test/CodeGen/Hexagon/expand-condsets-def-undef.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/expand-condsets-def-undef.mir?rev=286377&r1=286376&r2=286377&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/expand-condsets-def-undef.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/expand-condsets-def-undef.mir Wed Nov 9 10:19:08 2016
@@ -3,7 +3,7 @@
# CHECK-LABEL: name: fred
# Make sure that <def,read-undef> is accounted for when validating moves
-# during predication. In the code below, %2.subreg_hireg is invalidated
+# during predication. In the code below, %2.isub_hi is invalidated
# by the C2_mux instruction, and so predicating the A2_addi as an argument
# to the C2_muxir should not happen.
@@ -32,10 +32,10 @@ body: |
%1 = COPY %r0
%2 = COPY %d0
; Check that this instruction is unchanged (remains unpredicated)
- ; CHECK: %3 = A2_addi %2.subreg_hireg, 1
- %3 = A2_addi %2.subreg_hireg, 1
- undef %2.subreg_loreg = C2_mux %0, %2.subreg_loreg, %1
- %2.subreg_hireg = C2_muxir %0, %3, 0
+ ; CHECK: %3 = A2_addi %2.isub_hi, 1
+ %3 = A2_addi %2.isub_hi, 1
+ undef %2.isub_lo = C2_mux %0, %2.isub_lo, %1
+ %2.isub_hi = C2_muxir %0, %3, 0
...
Modified: llvm/trunk/test/CodeGen/Hexagon/regalloc-bad-undef.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/regalloc-bad-undef.mir?rev=286377&r1=286376&r2=286377&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/regalloc-bad-undef.mir (original)
+++ llvm/trunk/test/CodeGen/Hexagon/regalloc-bad-undef.mir Wed Nov 9 10:19:08 2016
@@ -146,11 +146,11 @@ body: |
successors: %bb.1.for.body
%59 = A2_tfrsi 524288
- undef %32.subreg_hireg = A2_tfrsi 0
+ undef %32.isub_hi = A2_tfrsi 0
%8 = S2_extractup undef %9, 6, 25
%47 = A2_tfrpi 2
%13 = A2_tfrpi -1
- %13 = S2_asl_r_p_acc %13, %47, %8.subreg_loreg
+ %13 = S2_asl_r_p_acc %13, %47, %8.isub_lo
%51 = A2_tfrpi 0
; CHECK: %d2 = S2_extractup undef %d0, 6, 25
@@ -164,25 +164,25 @@ body: |
ADJCALLSTACKDOWN 0, implicit-def dead %r29, implicit-def dead %r30, implicit %r31, implicit %r30, implicit %r29
J2_call @lrand48, implicit-def dead %d0, implicit-def dead %d1, implicit-def dead %d2, implicit-def dead %d3, implicit-def dead %d4, implicit-def dead %d5, implicit-def dead %d6, implicit-def dead %d7, implicit-def dead %r28, implicit-def dead %r31, implicit-def dead %p0, implicit-def dead %p1, implicit-def dead %p2, implicit-def dead %p3, implicit-def dead %m0, implicit-def dead %m1, implicit-def dead %lc0, implicit-def dead %lc1, implicit-def dead %sa0, implicit-def dead %sa1, implicit-def dead %usr, implicit-def %usr_ovf, implicit-def dead %cs0, implicit-def dead %cs1, implicit-def dead %w0, implicit-def dead %w1, implicit-def dead %w2, implicit-def dead %w3, implicit-def dead %w4, implicit-def dead %w5, implicit-def dead %w6, implicit-def dead %w7, implicit-def dead %w8, implicit-def dead %w9, implicit-def dead %w10, implicit-def dead %w11, implicit-def dead %w12, implicit-def dead %w13, implicit-def dead %w14, implicit-def dead %w15, implicit-def dead %q0, implicit-def dead
%q1, implicit-def dead %q2, implicit-def dead %q3, implicit-def %r0
ADJCALLSTACKUP 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit-def dead %r31, implicit %r29
- undef %29.subreg_loreg = COPY killed %r0
- %29.subreg_hireg = S2_asr_i_r %29.subreg_loreg, 31
+ undef %29.isub_lo = COPY killed %r0
+ %29.isub_hi = S2_asr_i_r %29.isub_lo, 31
ADJCALLSTACKDOWN 0, implicit-def dead %r29, implicit-def dead %r30, implicit %r31, implicit %r30, implicit %r29
J2_call @lrand48, implicit-def dead %d0, implicit-def dead %d1, implicit-def dead %d2, implicit-def dead %d3, implicit-def dead %d4, implicit-def dead %d5, implicit-def dead %d6, implicit-def dead %d7, implicit-def dead %r28, implicit-def dead %r31, implicit-def dead %p0, implicit-def dead %p1, implicit-def dead %p2, implicit-def dead %p3, implicit-def dead %m0, implicit-def dead %m1, implicit-def dead %lc0, implicit-def dead %lc1, implicit-def dead %sa0, implicit-def dead %sa1, implicit-def dead %usr, implicit-def %usr_ovf, implicit-def dead %cs0, implicit-def dead %cs1, implicit-def dead %w0, implicit-def dead %w1, implicit-def dead %w2, implicit-def dead %w3, implicit-def dead %w4, implicit-def dead %w5, implicit-def dead %w6, implicit-def dead %w7, implicit-def dead %w8, implicit-def dead %w9, implicit-def dead %w10, implicit-def dead %w11, implicit-def dead %w12, implicit-def dead %w13, implicit-def dead %w14, implicit-def dead %w15, implicit-def dead %q0, implicit-def dead
%q1, implicit-def dead %q2, implicit-def dead %q3, implicit-def %r0
ADJCALLSTACKUP 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit-def dead %r31, implicit %r29
- %32.subreg_loreg = COPY killed %r0
+ %32.isub_lo = COPY killed %r0
%7 = S2_extractup %32, 22, 9
ADJCALLSTACKDOWN 0, implicit-def dead %r29, implicit-def dead %r30, implicit %r31, implicit %r30, implicit %r29
J2_call @lrand48, implicit-def dead %d0, implicit-def dead %d1, implicit-def dead %d2, implicit-def dead %d3, implicit-def dead %d4, implicit-def dead %d5, implicit-def dead %d6, implicit-def dead %d7, implicit-def dead %r28, implicit-def dead %r31, implicit-def dead %p0, implicit-def dead %p1, implicit-def dead %p2, implicit-def dead %p3, implicit-def dead %m0, implicit-def dead %m1, implicit-def dead %lc0, implicit-def dead %lc1, implicit-def dead %sa0, implicit-def dead %sa1, implicit-def dead %usr, implicit-def %usr_ovf, implicit-def dead %cs0, implicit-def dead %cs1, implicit-def dead %w0, implicit-def dead %w1, implicit-def dead %w2, implicit-def dead %w3, implicit-def dead %w4, implicit-def dead %w5, implicit-def dead %w6, implicit-def dead %w7, implicit-def dead %w8, implicit-def dead %w9, implicit-def dead %w10, implicit-def dead %w11, implicit-def dead %w12, implicit-def dead %w13, implicit-def dead %w14, implicit-def dead %w15, implicit-def dead %q0, implicit-def dead
%q1, implicit-def dead %q2, implicit-def dead %q3, implicit-def %r0
ADJCALLSTACKUP 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit-def dead %r31, implicit %r29
- undef %43.subreg_loreg = COPY killed %r0
- %43.subreg_hireg = COPY %32.subreg_hireg
+ undef %43.isub_lo = COPY killed %r0
+ %43.isub_hi = COPY %32.isub_hi
%16 = S2_extractup %43, 6, 25
%18 = A2_tfrpi -1
- %18 = S2_asl_r_p_acc %18, %47, %16.subreg_loreg
+ %18 = S2_asl_r_p_acc %18, %47, %16.isub_lo
ADJCALLSTACKDOWN 0, implicit-def dead %r29, implicit-def dead %r30, implicit %r31, implicit %r30, implicit %r29
J2_call @lrand48, implicit-def dead %d0, implicit-def dead %d1, implicit-def dead %d2, implicit-def dead %d3, implicit-def dead %d4, implicit-def dead %d5, implicit-def dead %d6, implicit-def dead %d7, implicit-def dead %r28, implicit-def dead %r31, implicit-def dead %p0, implicit-def dead %p1, implicit-def dead %p2, implicit-def dead %p3, implicit-def dead %m0, implicit-def dead %m1, implicit-def dead %lc0, implicit-def dead %lc1, implicit-def dead %sa0, implicit-def dead %sa1, implicit-def dead %usr, implicit-def %usr_ovf, implicit-def dead %cs0, implicit-def dead %cs1, implicit-def dead %w0, implicit-def dead %w1, implicit-def dead %w2, implicit-def dead %w3, implicit-def dead %w4, implicit-def dead %w5, implicit-def dead %w6, implicit-def dead %w7, implicit-def dead %w8, implicit-def dead %w9, implicit-def dead %w10, implicit-def dead %w11, implicit-def dead %w12, implicit-def dead %w13, implicit-def dead %w14, implicit-def dead %w15, implicit-def dead %q0, implicit-def dead
%q1, implicit-def dead %q2, implicit-def dead %q3
ADJCALLSTACKUP 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit-def dead %r31, implicit %r29
- %22 = S2_asl_r_p %18, %8.subreg_loreg
+ %22 = S2_asl_r_p %18, %8.isub_lo
%21 = COPY %13
%21 = S2_lsr_i_p_and %21, %29, 9
%22 = S2_asl_i_p_and %22, %7, 42
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