[llvm] r286267 - [SystemZ] Refactor InstRR* instruction format patterns
Ulrich Weigand via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 8 10:36:31 PST 2016
Author: uweigand
Date: Tue Nov 8 12:36:31 2016
New Revision: 286267
URL: http://llvm.org/viewvc/llvm-project?rev=286267&view=rev
Log:
[SystemZ] Refactor InstRR* instruction format patterns
This changes the InstRR (and related) patterns to no longer
automatically add an "r" at the end of the mnemonic. This
makes the .td files more obviously understandable, and also
allows using the patterns for those few instructions that
do not follow the *r scheme.
Also add some more sub-formats of the RRF format class, to
match operand names and sequence from the PoP better.
No functional change.
Modified:
llvm/trunk/lib/Target/SystemZ/SystemZInstrFP.td
llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrFP.td?rev=286267&r1=286266&r2=286267&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrFP.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrFP.td Tue Nov 8 12:36:31 2016
@@ -34,21 +34,21 @@ let hasSideEffects = 0, isAsCheapAsAMove
// Moves between two floating-point registers.
let hasSideEffects = 0 in {
- def LER : UnaryRR <"le", 0x38, null_frag, FP32, FP32>;
- def LDR : UnaryRR <"ld", 0x28, null_frag, FP64, FP64>;
- def LXR : UnaryRRE<"lx", 0xB365, null_frag, FP128, FP128>;
+ def LER : UnaryRR <"ler", 0x38, null_frag, FP32, FP32>;
+ def LDR : UnaryRR <"ldr", 0x28, null_frag, FP64, FP64>;
+ def LXR : UnaryRRE<"lxr", 0xB365, null_frag, FP128, FP128>;
// For z13 we prefer LDR over LER to avoid partial register dependencies.
let isCodeGenOnly = 1 in
- def LDR32 : UnaryRR<"ld", 0x28, null_frag, FP32, FP32>;
+ def LDR32 : UnaryRR<"ldr", 0x28, null_frag, FP32, FP32>;
}
// Moves between two floating-point registers that also set the condition
// codes.
let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
- defm LTEBR : LoadAndTestRRE<"lteb", 0xB302, FP32>;
- defm LTDBR : LoadAndTestRRE<"ltdb", 0xB312, FP64>;
- defm LTXBR : LoadAndTestRRE<"ltxb", 0xB342, FP128>;
+ defm LTEBR : LoadAndTestRRE<"ltebr", 0xB302, FP32>;
+ defm LTDBR : LoadAndTestRRE<"ltdbr", 0xB312, FP64>;
+ defm LTXBR : LoadAndTestRRE<"ltxbr", 0xB342, FP128>;
}
// Note that LTxBRCompare is not available if we have vector support,
// since load-and-test instructions will partially clobber the target
@@ -73,13 +73,13 @@ let Predicates = [FeatureVector] in {
}
// Moves between 64-bit integer and floating-point registers.
-def LGDR : UnaryRRE<"lgd", 0xB3CD, bitconvert, GR64, FP64>;
-def LDGR : UnaryRRE<"ldg", 0xB3C1, bitconvert, FP64, GR64>;
+def LGDR : UnaryRRE<"lgdr", 0xB3CD, bitconvert, GR64, FP64>;
+def LDGR : UnaryRRE<"ldgr", 0xB3C1, bitconvert, FP64, GR64>;
// fcopysign with an FP32 result.
let isCodeGenOnly = 1 in {
- def CPSDRss : BinaryRRF<"cpsd", 0xB372, fcopysign, FP32, FP32>;
- def CPSDRsd : BinaryRRF<"cpsd", 0xB372, fcopysign, FP32, FP64>;
+ def CPSDRss : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP32, FP32, FP32>;
+ def CPSDRsd : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP32, FP32, FP64>;
}
// The sign of an FP128 is in the high register.
@@ -88,8 +88,8 @@ def : Pat<(fcopysign FP32:$src1, FP128:$
// fcopysign with an FP64 result.
let isCodeGenOnly = 1 in
- def CPSDRds : BinaryRRF<"cpsd", 0xB372, fcopysign, FP64, FP32>;
-def CPSDRdd : BinaryRRF<"cpsd", 0xB372, fcopysign, FP64, FP64>;
+ def CPSDRds : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP64, FP64, FP32>;
+def CPSDRdd : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP64, FP64, FP64>;
// The sign of an FP128 is in the high register.
def : Pat<(fcopysign FP64:$src1, FP128:$src2),
@@ -154,15 +154,15 @@ let SimpleBDXStore = 1 in {
// Convert floating-point values to narrower representations, rounding
// according to the current mode. The destination of LEXBR and LDXBR
// is a 128-bit value, but only the first register of the pair is used.
-def LEDBR : UnaryRRE<"ledb", 0xB344, fpround, FP32, FP64>;
-def LEXBR : UnaryRRE<"lexb", 0xB346, null_frag, FP128, FP128>;
-def LDXBR : UnaryRRE<"ldxb", 0xB345, null_frag, FP128, FP128>;
+def LEDBR : UnaryRRE<"ledbr", 0xB344, fpround, FP32, FP64>;
+def LEXBR : UnaryRRE<"lexbr", 0xB346, null_frag, FP128, FP128>;
+def LDXBR : UnaryRRE<"ldxbr", 0xB345, null_frag, FP128, FP128>;
-def LEDBRA : UnaryRRF4<"ledbra", 0xB344, FP32, FP64>,
+def LEDBRA : TernaryRRFe<"ledbra", 0xB344, FP32, FP64>,
Requires<[FeatureFPExtension]>;
-def LEXBRA : UnaryRRF4<"lexbra", 0xB346, FP128, FP128>,
+def LEXBRA : TernaryRRFe<"lexbra", 0xB346, FP128, FP128>,
Requires<[FeatureFPExtension]>;
-def LDXBRA : UnaryRRF4<"ldxbra", 0xB345, FP128, FP128>,
+def LDXBRA : TernaryRRFe<"ldxbra", 0xB345, FP128, FP128>,
Requires<[FeatureFPExtension]>;
def : Pat<(f32 (fpround FP128:$src)),
@@ -171,9 +171,9 @@ def : Pat<(f64 (fpround FP128:$src)),
(EXTRACT_SUBREG (LDXBR FP128:$src), subreg_h64)>;
// Extend register floating-point values to wider representations.
-def LDEBR : UnaryRRE<"ldeb", 0xB304, fpextend, FP64, FP32>;
-def LXEBR : UnaryRRE<"lxeb", 0xB306, fpextend, FP128, FP32>;
-def LXDBR : UnaryRRE<"lxdb", 0xB305, fpextend, FP128, FP64>;
+def LDEBR : UnaryRRE<"ldebr", 0xB304, fpextend, FP64, FP32>;
+def LXEBR : UnaryRRE<"lxebr", 0xB306, fpextend, FP128, FP32>;
+def LXDBR : UnaryRRE<"lxdbr", 0xB305, fpextend, FP128, FP64>;
// Extend memory floating-point values to wider representations.
def LDEB : UnaryRXE<"ldeb", 0xED04, extloadf32, FP64, 4>;
@@ -181,23 +181,23 @@ def LXEB : UnaryRXE<"lxeb", 0xED06, extl
def LXDB : UnaryRXE<"lxdb", 0xED05, extloadf64, FP128, 8>;
// Convert a signed integer register value to a floating-point one.
-def CEFBR : UnaryRRE<"cefb", 0xB394, sint_to_fp, FP32, GR32>;
-def CDFBR : UnaryRRE<"cdfb", 0xB395, sint_to_fp, FP64, GR32>;
-def CXFBR : UnaryRRE<"cxfb", 0xB396, sint_to_fp, FP128, GR32>;
-
-def CEGBR : UnaryRRE<"cegb", 0xB3A4, sint_to_fp, FP32, GR64>;
-def CDGBR : UnaryRRE<"cdgb", 0xB3A5, sint_to_fp, FP64, GR64>;
-def CXGBR : UnaryRRE<"cxgb", 0xB3A6, sint_to_fp, FP128, GR64>;
+def CEFBR : UnaryRRE<"cefbr", 0xB394, sint_to_fp, FP32, GR32>;
+def CDFBR : UnaryRRE<"cdfbr", 0xB395, sint_to_fp, FP64, GR32>;
+def CXFBR : UnaryRRE<"cxfbr", 0xB396, sint_to_fp, FP128, GR32>;
+
+def CEGBR : UnaryRRE<"cegbr", 0xB3A4, sint_to_fp, FP32, GR64>;
+def CDGBR : UnaryRRE<"cdgbr", 0xB3A5, sint_to_fp, FP64, GR64>;
+def CXGBR : UnaryRRE<"cxgbr", 0xB3A6, sint_to_fp, FP128, GR64>;
// Convert am unsigned integer register value to a floating-point one.
let Predicates = [FeatureFPExtension] in {
- def CELFBR : UnaryRRF4<"celfbr", 0xB390, FP32, GR32>;
- def CDLFBR : UnaryRRF4<"cdlfbr", 0xB391, FP64, GR32>;
- def CXLFBR : UnaryRRF4<"cxlfbr", 0xB392, FP128, GR32>;
-
- def CELGBR : UnaryRRF4<"celgbr", 0xB3A0, FP32, GR64>;
- def CDLGBR : UnaryRRF4<"cdlgbr", 0xB3A1, FP64, GR64>;
- def CXLGBR : UnaryRRF4<"cxlgbr", 0xB3A2, FP128, GR64>;
+ def CELFBR : TernaryRRFe<"celfbr", 0xB390, FP32, GR32>;
+ def CDLFBR : TernaryRRFe<"cdlfbr", 0xB391, FP64, GR32>;
+ def CXLFBR : TernaryRRFe<"cxlfbr", 0xB392, FP128, GR32>;
+
+ def CELGBR : TernaryRRFe<"celgbr", 0xB3A0, FP32, GR64>;
+ def CDLGBR : TernaryRRFe<"cdlgbr", 0xB3A1, FP64, GR64>;
+ def CXLGBR : TernaryRRFe<"cxlgbr", 0xB3A2, FP128, GR64>;
def : Pat<(f32 (uint_to_fp GR32:$src)), (CELFBR 0, GR32:$src, 0)>;
def : Pat<(f64 (uint_to_fp GR32:$src)), (CDLFBR 0, GR32:$src, 0)>;
@@ -211,13 +211,13 @@ let Predicates = [FeatureFPExtension] in
// Convert a floating-point register value to a signed integer value,
// with the second operand (modifier M3) specifying the rounding mode.
let Defs = [CC] in {
- def CFEBR : UnaryRRF<"cfeb", 0xB398, GR32, FP32>;
- def CFDBR : UnaryRRF<"cfdb", 0xB399, GR32, FP64>;
- def CFXBR : UnaryRRF<"cfxb", 0xB39A, GR32, FP128>;
-
- def CGEBR : UnaryRRF<"cgeb", 0xB3A8, GR64, FP32>;
- def CGDBR : UnaryRRF<"cgdb", 0xB3A9, GR64, FP64>;
- def CGXBR : UnaryRRF<"cgxb", 0xB3AA, GR64, FP128>;
+ def CFEBR : BinaryRRFe<"cfebr", 0xB398, GR32, FP32>;
+ def CFDBR : BinaryRRFe<"cfdbr", 0xB399, GR32, FP64>;
+ def CFXBR : BinaryRRFe<"cfxbr", 0xB39A, GR32, FP128>;
+
+ def CGEBR : BinaryRRFe<"cgebr", 0xB3A8, GR64, FP32>;
+ def CGDBR : BinaryRRFe<"cgdbr", 0xB3A9, GR64, FP64>;
+ def CGXBR : BinaryRRFe<"cgxbr", 0xB3AA, GR64, FP128>;
}
// fp_to_sint always rounds towards zero, which is modifier value 5.
@@ -232,13 +232,13 @@ def : Pat<(i64 (fp_to_sint FP128:$src)),
// Convert a floating-point register value to an unsigned integer value.
let Predicates = [FeatureFPExtension] in {
let Defs = [CC] in {
- def CLFEBR : UnaryRRF4<"clfebr", 0xB39C, GR32, FP32>;
- def CLFDBR : UnaryRRF4<"clfdbr", 0xB39D, GR32, FP64>;
- def CLFXBR : UnaryRRF4<"clfxbr", 0xB39E, GR32, FP128>;
-
- def CLGEBR : UnaryRRF4<"clgebr", 0xB3AC, GR64, FP32>;
- def CLGDBR : UnaryRRF4<"clgdbr", 0xB3AD, GR64, FP64>;
- def CLGXBR : UnaryRRF4<"clgxbr", 0xB3AE, GR64, FP128>;
+ def CLFEBR : TernaryRRFe<"clfebr", 0xB39C, GR32, FP32>;
+ def CLFDBR : TernaryRRFe<"clfdbr", 0xB39D, GR32, FP64>;
+ def CLFXBR : TernaryRRFe<"clfxbr", 0xB39E, GR32, FP128>;
+
+ def CLGEBR : TernaryRRFe<"clgebr", 0xB3AC, GR64, FP32>;
+ def CLGDBR : TernaryRRFe<"clgdbr", 0xB3AD, GR64, FP64>;
+ def CLGXBR : TernaryRRFe<"clgxbr", 0xB3AE, GR64, FP128>;
}
def : Pat<(i32 (fp_to_uint FP32:$src)), (CLFEBR 5, FP32:$src, 0)>;
@@ -265,50 +265,50 @@ let Predicates = [FeatureFPExtension] in
// Negation (Load Complement).
let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
- def LCEBR : UnaryRRE<"lceb", 0xB303, null_frag, FP32, FP32>;
- def LCDBR : UnaryRRE<"lcdb", 0xB313, null_frag, FP64, FP64>;
- def LCXBR : UnaryRRE<"lcxb", 0xB343, fneg, FP128, FP128>;
+ def LCEBR : UnaryRRE<"lcebr", 0xB303, null_frag, FP32, FP32>;
+ def LCDBR : UnaryRRE<"lcdbr", 0xB313, null_frag, FP64, FP64>;
+ def LCXBR : UnaryRRE<"lcxbr", 0xB343, fneg, FP128, FP128>;
}
// Generic form, which does not set CC.
-def LCDFR : UnaryRRE<"lcdf", 0xB373, fneg, FP64, FP64>;
+def LCDFR : UnaryRRE<"lcdfr", 0xB373, fneg, FP64, FP64>;
let isCodeGenOnly = 1 in
- def LCDFR_32 : UnaryRRE<"lcdf", 0xB373, fneg, FP32, FP32>;
+ def LCDFR_32 : UnaryRRE<"lcdfr", 0xB373, fneg, FP32, FP32>;
// Absolute value (Load Positive).
let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
- def LPEBR : UnaryRRE<"lpeb", 0xB300, null_frag, FP32, FP32>;
- def LPDBR : UnaryRRE<"lpdb", 0xB310, null_frag, FP64, FP64>;
- def LPXBR : UnaryRRE<"lpxb", 0xB340, fabs, FP128, FP128>;
+ def LPEBR : UnaryRRE<"lpebr", 0xB300, null_frag, FP32, FP32>;
+ def LPDBR : UnaryRRE<"lpdbr", 0xB310, null_frag, FP64, FP64>;
+ def LPXBR : UnaryRRE<"lpxbr", 0xB340, fabs, FP128, FP128>;
}
// Generic form, which does not set CC.
-def LPDFR : UnaryRRE<"lpdf", 0xB370, fabs, FP64, FP64>;
+def LPDFR : UnaryRRE<"lpdfr", 0xB370, fabs, FP64, FP64>;
let isCodeGenOnly = 1 in
- def LPDFR_32 : UnaryRRE<"lpdf", 0xB370, fabs, FP32, FP32>;
+ def LPDFR_32 : UnaryRRE<"lpdfr", 0xB370, fabs, FP32, FP32>;
// Negative absolute value (Load Negative).
let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
- def LNEBR : UnaryRRE<"lneb", 0xB301, null_frag, FP32, FP32>;
- def LNDBR : UnaryRRE<"lndb", 0xB311, null_frag, FP64, FP64>;
- def LNXBR : UnaryRRE<"lnxb", 0xB341, fnabs, FP128, FP128>;
+ def LNEBR : UnaryRRE<"lnebr", 0xB301, null_frag, FP32, FP32>;
+ def LNDBR : UnaryRRE<"lndbr", 0xB311, null_frag, FP64, FP64>;
+ def LNXBR : UnaryRRE<"lnxbr", 0xB341, fnabs, FP128, FP128>;
}
// Generic form, which does not set CC.
-def LNDFR : UnaryRRE<"lndf", 0xB371, fnabs, FP64, FP64>;
+def LNDFR : UnaryRRE<"lndfr", 0xB371, fnabs, FP64, FP64>;
let isCodeGenOnly = 1 in
- def LNDFR_32 : UnaryRRE<"lndf", 0xB371, fnabs, FP32, FP32>;
+ def LNDFR_32 : UnaryRRE<"lndfr", 0xB371, fnabs, FP32, FP32>;
// Square root.
-def SQEBR : UnaryRRE<"sqeb", 0xB314, fsqrt, FP32, FP32>;
-def SQDBR : UnaryRRE<"sqdb", 0xB315, fsqrt, FP64, FP64>;
-def SQXBR : UnaryRRE<"sqxb", 0xB316, fsqrt, FP128, FP128>;
+def SQEBR : UnaryRRE<"sqebr", 0xB314, fsqrt, FP32, FP32>;
+def SQDBR : UnaryRRE<"sqdbr", 0xB315, fsqrt, FP64, FP64>;
+def SQXBR : UnaryRRE<"sqxbr", 0xB316, fsqrt, FP128, FP128>;
def SQEB : UnaryRXE<"sqeb", 0xED14, loadu<fsqrt>, FP32, 4>;
def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<fsqrt>, FP64, 8>;
// Round to an integer, with the second operand (modifier M3) specifying
// the rounding mode. These forms always check for inexact conditions.
-def FIEBR : UnaryRRF<"fieb", 0xB357, FP32, FP32>;
-def FIDBR : UnaryRRF<"fidb", 0xB35F, FP64, FP64>;
-def FIXBR : UnaryRRF<"fixb", 0xB347, FP128, FP128>;
+def FIEBR : BinaryRRFe<"fiebr", 0xB357, FP32, FP32>;
+def FIDBR : BinaryRRFe<"fidbr", 0xB35F, FP64, FP64>;
+def FIXBR : BinaryRRFe<"fixbr", 0xB347, FP128, FP128>;
// frint rounds according to the current mode (modifier 0) and detects
// inexact conditions.
@@ -319,9 +319,9 @@ def : Pat<(frint FP128:$src), (FIXBR 0,
let Predicates = [FeatureFPExtension] in {
// Extended forms of the FIxBR instructions. M4 can be set to 4
// to suppress detection of inexact conditions.
- def FIEBRA : UnaryRRF4<"fiebra", 0xB357, FP32, FP32>;
- def FIDBRA : UnaryRRF4<"fidbra", 0xB35F, FP64, FP64>;
- def FIXBRA : UnaryRRF4<"fixbra", 0xB347, FP128, FP128>;
+ def FIEBRA : TernaryRRFe<"fiebra", 0xB357, FP32, FP32>;
+ def FIDBRA : TernaryRRFe<"fidbra", 0xB35F, FP64, FP64>;
+ def FIXBRA : TernaryRRFe<"fixbra", 0xB347, FP128, FP128>;
// fnearbyint is like frint but does not detect inexact conditions.
def : Pat<(fnearbyint FP32:$src), (FIEBRA 0, FP32:$src, 4)>;
@@ -359,9 +359,9 @@ let Predicates = [FeatureFPExtension] in
// Addition.
let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
let isCommutable = 1 in {
- def AEBR : BinaryRRE<"aeb", 0xB30A, fadd, FP32, FP32>;
- def ADBR : BinaryRRE<"adb", 0xB31A, fadd, FP64, FP64>;
- def AXBR : BinaryRRE<"axb", 0xB34A, fadd, FP128, FP128>;
+ def AEBR : BinaryRRE<"aebr", 0xB30A, fadd, FP32, FP32>;
+ def ADBR : BinaryRRE<"adbr", 0xB31A, fadd, FP64, FP64>;
+ def AXBR : BinaryRRE<"axbr", 0xB34A, fadd, FP128, FP128>;
}
def AEB : BinaryRXE<"aeb", 0xED0A, fadd, FP32, load, 4>;
def ADB : BinaryRXE<"adb", 0xED1A, fadd, FP64, load, 8>;
@@ -369,9 +369,9 @@ let Defs = [CC], CCValues = 0xF, Compare
// Subtraction.
let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
- def SEBR : BinaryRRE<"seb", 0xB30B, fsub, FP32, FP32>;
- def SDBR : BinaryRRE<"sdb", 0xB31B, fsub, FP64, FP64>;
- def SXBR : BinaryRRE<"sxb", 0xB34B, fsub, FP128, FP128>;
+ def SEBR : BinaryRRE<"sebr", 0xB30B, fsub, FP32, FP32>;
+ def SDBR : BinaryRRE<"sdbr", 0xB31B, fsub, FP64, FP64>;
+ def SXBR : BinaryRRE<"sxbr", 0xB34B, fsub, FP128, FP128>;
def SEB : BinaryRXE<"seb", 0xED0B, fsub, FP32, load, 4>;
def SDB : BinaryRXE<"sdb", 0xED1B, fsub, FP64, load, 8>;
@@ -379,15 +379,15 @@ let Defs = [CC], CCValues = 0xF, Compare
// Multiplication.
let isCommutable = 1 in {
- def MEEBR : BinaryRRE<"meeb", 0xB317, fmul, FP32, FP32>;
- def MDBR : BinaryRRE<"mdb", 0xB31C, fmul, FP64, FP64>;
- def MXBR : BinaryRRE<"mxb", 0xB34C, fmul, FP128, FP128>;
+ def MEEBR : BinaryRRE<"meebr", 0xB317, fmul, FP32, FP32>;
+ def MDBR : BinaryRRE<"mdbr", 0xB31C, fmul, FP64, FP64>;
+ def MXBR : BinaryRRE<"mxbr", 0xB34C, fmul, FP128, FP128>;
}
def MEEB : BinaryRXE<"meeb", 0xED17, fmul, FP32, load, 4>;
def MDB : BinaryRXE<"mdb", 0xED1C, fmul, FP64, load, 8>;
// f64 multiplication of two FP32 registers.
-def MDEBR : BinaryRRE<"mdeb", 0xB30C, null_frag, FP64, FP32>;
+def MDEBR : BinaryRRE<"mdebr", 0xB30C, null_frag, FP64, FP32>;
def : Pat<(fmul (f64 (fpextend FP32:$src1)), (f64 (fpextend FP32:$src2))),
(MDEBR (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
FP32:$src1, subreg_r32), FP32:$src2)>;
@@ -400,7 +400,7 @@ def : Pat<(fmul (f64 (fpextend FP32:$src
bdxaddr12only:$addr)>;
// f128 multiplication of two FP64 registers.
-def MXDBR : BinaryRRE<"mxdb", 0xB307, null_frag, FP128, FP64>;
+def MXDBR : BinaryRRE<"mxdbr", 0xB307, null_frag, FP128, FP64>;
def : Pat<(fmul (f128 (fpextend FP64:$src1)), (f128 (fpextend FP64:$src2))),
(MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)),
FP64:$src1, subreg_h64), FP64:$src2)>;
@@ -413,23 +413,23 @@ def : Pat<(fmul (f128 (fpextend FP64:$sr
bdxaddr12only:$addr)>;
// Fused multiply-add.
-def MAEBR : TernaryRRD<"maeb", 0xB30E, z_fma, FP32>;
-def MADBR : TernaryRRD<"madb", 0xB31E, z_fma, FP64>;
+def MAEBR : TernaryRRD<"maebr", 0xB30E, z_fma, FP32>;
+def MADBR : TernaryRRD<"madbr", 0xB31E, z_fma, FP64>;
def MAEB : TernaryRXF<"maeb", 0xED0E, z_fma, FP32, load, 4>;
def MADB : TernaryRXF<"madb", 0xED1E, z_fma, FP64, load, 8>;
// Fused multiply-subtract.
-def MSEBR : TernaryRRD<"mseb", 0xB30F, z_fms, FP32>;
-def MSDBR : TernaryRRD<"msdb", 0xB31F, z_fms, FP64>;
+def MSEBR : TernaryRRD<"msebr", 0xB30F, z_fms, FP32>;
+def MSDBR : TernaryRRD<"msdbr", 0xB31F, z_fms, FP64>;
def MSEB : TernaryRXF<"mseb", 0xED0F, z_fms, FP32, load, 4>;
def MSDB : TernaryRXF<"msdb", 0xED1F, z_fms, FP64, load, 8>;
// Division.
-def DEBR : BinaryRRE<"deb", 0xB30D, fdiv, FP32, FP32>;
-def DDBR : BinaryRRE<"ddb", 0xB31D, fdiv, FP64, FP64>;
-def DXBR : BinaryRRE<"dxb", 0xB34D, fdiv, FP128, FP128>;
+def DEBR : BinaryRRE<"debr", 0xB30D, fdiv, FP32, FP32>;
+def DDBR : BinaryRRE<"ddbr", 0xB31D, fdiv, FP64, FP64>;
+def DXBR : BinaryRRE<"dxbr", 0xB34D, fdiv, FP128, FP128>;
def DEB : BinaryRXE<"deb", 0xED0D, fdiv, FP32, load, 4>;
def DDB : BinaryRXE<"ddb", 0xED1D, fdiv, FP64, load, 8>;
@@ -439,9 +439,9 @@ def DDB : BinaryRXE<"ddb", 0xED1D, fdiv,
//===----------------------------------------------------------------------===//
let Defs = [CC], CCValues = 0xF in {
- def CEBR : CompareRRE<"ceb", 0xB309, z_fcmp, FP32, FP32>;
- def CDBR : CompareRRE<"cdb", 0xB319, z_fcmp, FP64, FP64>;
- def CXBR : CompareRRE<"cxb", 0xB349, z_fcmp, FP128, FP128>;
+ def CEBR : CompareRRE<"cebr", 0xB309, z_fcmp, FP32, FP32>;
+ def CDBR : CompareRRE<"cdbr", 0xB319, z_fcmp, FP64, FP64>;
+ def CXBR : CompareRRE<"cxbr", 0xB349, z_fcmp, FP128, FP128>;
def CEB : CompareRXE<"ceb", 0xED09, z_fcmp, FP32, load, 4>;
def CDB : CompareRXE<"cdb", 0xED19, z_fcmp, FP64, load, 8>;
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td?rev=286267&r1=286266&r2=286267&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td Tue Nov 8 12:36:31 2016
@@ -29,7 +29,7 @@ class InstSystemZ<int size, dag outs, da
string DispSize = "none";
// Many register-based <INSN>R instructions have a memory-based <INSN>
- // counterpart. OpKey uniquely identifies <INSN>, while OpType is
+ // counterpart. OpKey uniquely identifies <INSN>R, while OpType is
// "reg" for <INSN>R and "mem" for <INSN>.
string OpKey = "";
string OpType = "none";
@@ -431,7 +431,7 @@ class InstRRE<bits<16> op, dag outs, dag
let Inst{3-0} = R2;
}
-class InstRRF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+class InstRRFa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<4, outs, ins, asmstr, pattern> {
field bits<32> Inst;
field bits<32> SoftFail = 0;
@@ -439,11 +439,28 @@ class InstRRF<bits<16> op, dag outs, dag
bits<4> R1;
bits<4> R2;
bits<4> R3;
- bits<4> R4;
+ bits<4> M4;
let Inst{31-16} = op;
let Inst{15-12} = R3;
- let Inst{11-8} = R4;
+ let Inst{11-8} = M4;
+ let Inst{7-4} = R1;
+ let Inst{3-0} = R2;
+}
+
+class InstRRFb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstSystemZ<4, outs, ins, asmstr, pattern> {
+ field bits<32> Inst;
+ field bits<32> SoftFail = 0;
+
+ bits<4> R1;
+ bits<4> R2;
+ bits<4> R3;
+ bits<4> M4;
+
+ let Inst{31-16} = op;
+ let Inst{15-12} = R3;
+ let Inst{11-8} = M4;
let Inst{7-4} = R1;
let Inst{3-0} = R2;
}
@@ -464,6 +481,23 @@ class InstRRFc<bits<16> op, dag outs, da
let Inst{3-0} = R2;
}
+class InstRRFe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstSystemZ<4, outs, ins, asmstr, pattern> {
+ field bits<32> Inst;
+ field bits<32> SoftFail = 0;
+
+ bits<4> R1;
+ bits<4> R2;
+ bits<4> M3;
+ bits<4> M4;
+
+ let Inst{31-16} = op;
+ let Inst{15-12} = M3;
+ let Inst{11-8} = M4;
+ let Inst{7-4} = R1;
+ let Inst{3-0} = R2;
+}
+
class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
@@ -1212,7 +1246,7 @@ class DirectiveInsnRRE<dag outs, dag ins
}
class DirectiveInsnRRF<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstRRF<0, outs, ins, asmstr, pattern> {
+ : InstRRFa<0, outs, ins, asmstr, pattern> {
bits<32> enc;
let Inst{31-16} = enc{31-16};
@@ -1872,7 +1906,7 @@ class StoreRX<string mnemonic, bits<8> o
: InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
mnemonic#"\t$R1, $XBD2",
[(operator cls:$R1, mode:$XBD2)]> {
- let OpKey = mnemonic ## cls;
+ let OpKey = mnemonic#"r"#cls;
let OpType = "mem";
let mayStore = 1;
let AccessBytes = bytes;
@@ -1884,7 +1918,7 @@ class StoreRXY<string mnemonic, bits<16>
: InstRXYa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
mnemonic#"\t$R1, $XBD2",
[(operator cls:$R1, mode:$XBD2)]> {
- let OpKey = mnemonic ## cls;
+ let OpKey = mnemonic#"r"#cls;
let OpType = "mem";
let mayStore = 1;
let AccessBytes = bytes;
@@ -2037,35 +2071,21 @@ multiclass CondStoreRSYPair<string mnemo
class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
RegisterOperand cls1, RegisterOperand cls2>
: InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2),
- mnemonic#"r\t$R1, $R2",
+ mnemonic#"\t$R1, $R2",
[(set cls1:$R1, (operator cls2:$R2))]> {
- let OpKey = mnemonic ## cls1;
+ let OpKey = mnemonic#cls1;
let OpType = "reg";
}
class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
RegisterOperand cls1, RegisterOperand cls2>
: InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2),
- mnemonic#"r\t$R1, $R2",
+ mnemonic#"\t$R1, $R2",
[(set cls1:$R1, (operator cls2:$R2))]> {
- let OpKey = mnemonic ## cls1;
+ let OpKey = mnemonic#cls1;
let OpType = "reg";
}
-class UnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
- RegisterOperand cls2>
- : InstRRF<opcode, (outs cls1:$R1), (ins imm32zx4:$R3, cls2:$R2),
- mnemonic#"r\t$R1, $R3, $R2", []> {
- let OpKey = mnemonic ## cls1;
- let OpType = "reg";
- let R4 = 0;
-}
-
-class UnaryRRF4<string mnemonic, bits<16> opcode, RegisterOperand cls1,
- RegisterOperand cls2>
- : InstRRF<opcode, (outs cls1:$R1), (ins imm32zx4:$R3, cls2:$R2, imm32zx4:$R4),
- mnemonic#"\t$R1, $R3, $R2, $R4", []>;
-
// These instructions are generated by if conversion. The old value of R1
// is added as an implicit use.
class CondUnaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
@@ -2220,7 +2240,7 @@ class UnaryRX<string mnemonic, bits<8> o
: InstRXa<opcode, (outs cls:$R1), (ins mode:$XBD2),
mnemonic#"\t$R1, $XBD2",
[(set cls:$R1, (operator mode:$XBD2))]> {
- let OpKey = mnemonic ## cls;
+ let OpKey = mnemonic#"r"#cls;
let OpType = "mem";
let mayLoad = 1;
let AccessBytes = bytes;
@@ -2231,7 +2251,7 @@ class UnaryRXE<string mnemonic, bits<16>
: InstRXE<opcode, (outs cls:$R1), (ins bdxaddr12only:$XBD2),
mnemonic#"\t$R1, $XBD2",
[(set cls:$R1, (operator bdxaddr12only:$XBD2))]> {
- let OpKey = mnemonic ## cls;
+ let OpKey = mnemonic#"r"#cls;
let OpType = "mem";
let mayLoad = 1;
let AccessBytes = bytes;
@@ -2244,7 +2264,7 @@ class UnaryRXY<string mnemonic, bits<16>
: InstRXYa<opcode, (outs cls:$R1), (ins mode:$XBD2),
mnemonic#"\t$R1, $XBD2",
[(set cls:$R1, (operator mode:$XBD2))]> {
- let OpKey = mnemonic ## cls;
+ let OpKey = mnemonic#"r"#cls;
let OpType = "mem";
let mayLoad = 1;
let AccessBytes = bytes;
@@ -2350,9 +2370,9 @@ class UnaryVRXGeneric<string mnemonic, b
class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
RegisterOperand cls1, RegisterOperand cls2>
: InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
- mnemonic#"r\t$R1, $R2",
+ mnemonic#"\t$R1, $R2",
[(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
- let OpKey = mnemonic ## cls1;
+ let OpKey = mnemonic#cls1;
let OpType = "reg";
let Constraints = "$R1 = $R1src";
let DisableEncoding = "$R1src";
@@ -2361,30 +2381,21 @@ class BinaryRR<string mnemonic, bits<8>
class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
RegisterOperand cls1, RegisterOperand cls2>
: InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
- mnemonic#"r\t$R1, $R2",
+ mnemonic#"\t$R1, $R2",
[(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
- let OpKey = mnemonic ## cls1;
+ let OpKey = mnemonic#cls1;
let OpType = "reg";
let Constraints = "$R1 = $R1src";
let DisableEncoding = "$R1src";
}
-class BinaryRRF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
- RegisterOperand cls1, RegisterOperand cls2>
- : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R2, cls2:$R3),
- mnemonic#"r\t$R1, $R3, $R2",
- [(set cls1:$R1, (operator cls1:$R2, cls2:$R3))]> {
- let OpKey = mnemonic ## cls1;
- let OpType = "reg";
- let R4 = 0;
-}
-
-class BinaryRRFK<string mnemonic, bits<16> opcode, SDPatternOperator operator,
- RegisterOperand cls1, RegisterOperand cls2>
- : InstRRF<opcode, (outs cls1:$R1), (ins cls1:$R2, cls2:$R3),
- mnemonic#"rk\t$R1, $R2, $R3",
- [(set cls1:$R1, (operator cls1:$R2, cls2:$R3))]> {
- let R4 = 0;
+class BinaryRRFa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
+ RegisterOperand cls1, RegisterOperand cls2,
+ RegisterOperand cls3>
+ : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3),
+ mnemonic#"\t$R1, $R2, $R3",
+ [(set cls1:$R1, (operator cls2:$R2, cls3:$R3))]> {
+ let M4 = 0;
}
multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
@@ -2392,7 +2403,7 @@ multiclass BinaryRRAndK<string mnemonic,
RegisterOperand cls2> {
let NumOpsKey = mnemonic in {
let NumOpsValue = "3" in
- def K : BinaryRRFK<mnemonic, opcode2, null_frag, cls1, cls2>,
+ def K : BinaryRRFa<mnemonic#"k", opcode2, null_frag, cls1, cls1, cls2>,
Requires<[FeatureDistinctOps]>;
let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
def "" : BinaryRR<mnemonic, opcode1, operator, cls1, cls2>;
@@ -2404,13 +2415,29 @@ multiclass BinaryRREAndK<string mnemonic
RegisterOperand cls2> {
let NumOpsKey = mnemonic in {
let NumOpsValue = "3" in
- def K : BinaryRRFK<mnemonic, opcode2, null_frag, cls1, cls2>,
+ def K : BinaryRRFa<mnemonic#"k", opcode2, null_frag, cls1, cls1, cls2>,
Requires<[FeatureDistinctOps]>;
let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
def "" : BinaryRRE<mnemonic, opcode1, operator, cls1, cls2>;
}
}
+class BinaryRRFb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
+ RegisterOperand cls1, RegisterOperand cls2,
+ RegisterOperand cls3>
+ : InstRRFb<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3),
+ mnemonic#"\t$R1, $R3, $R2",
+ [(set cls1:$R1, (operator cls2:$R2, cls3:$R3))]> {
+ let M4 = 0;
+}
+
+class BinaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1,
+ RegisterOperand cls2>
+ : InstRRFe<opcode, (outs cls1:$R1), (ins imm32zx4:$M3, cls2:$R2),
+ mnemonic#"\t$R1, $M3, $R2", []> {
+ let M4 = 0;
+}
+
class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
RegisterOperand cls, Immediate imm>
: InstRIa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
@@ -2480,7 +2507,7 @@ class BinaryRX<string mnemonic, bits<8>
: InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
mnemonic#"\t$R1, $XBD2",
[(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
- let OpKey = mnemonic ## cls;
+ let OpKey = mnemonic#"r"#cls;
let OpType = "mem";
let Constraints = "$R1 = $R1src";
let DisableEncoding = "$R1src";
@@ -2494,7 +2521,7 @@ class BinaryRXE<string mnemonic, bits<16
mnemonic#"\t$R1, $XBD2",
[(set cls:$R1, (operator cls:$R1src,
(load bdxaddr12only:$XBD2)))]> {
- let OpKey = mnemonic ## cls;
+ let OpKey = mnemonic#"r"#cls;
let OpType = "mem";
let Constraints = "$R1 = $R1src";
let DisableEncoding = "$R1src";
@@ -2509,7 +2536,7 @@ class BinaryRXY<string mnemonic, bits<16
: InstRXYa<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
mnemonic#"\t$R1, $XBD2",
[(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
- let OpKey = mnemonic ## cls;
+ let OpKey = mnemonic#"r"#cls;
let OpType = "mem";
let Constraints = "$R1 = $R1src";
let DisableEncoding = "$R1src";
@@ -2797,9 +2824,9 @@ class StoreBinaryVRX<string mnemonic, bi
class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
RegisterOperand cls1, RegisterOperand cls2>
: InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2),
- mnemonic#"r\t$R1, $R2",
+ mnemonic#"\t$R1, $R2",
[(operator cls1:$R1, cls2:$R2)]> {
- let OpKey = mnemonic ## cls1;
+ let OpKey = mnemonic#cls1;
let OpType = "reg";
let isCompare = 1;
}
@@ -2807,9 +2834,9 @@ class CompareRR<string mnemonic, bits<8>
class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
RegisterOperand cls1, RegisterOperand cls2>
: InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
- mnemonic#"r\t$R1, $R2",
+ mnemonic#"\t$R1, $R2",
[(operator cls1:$R1, cls2:$R2)]> {
- let OpKey = mnemonic ## cls1;
+ let OpKey = mnemonic#cls1;
let OpType = "reg";
let isCompare = 1;
}
@@ -2849,7 +2876,7 @@ class CompareRX<string mnemonic, bits<8>
: InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
mnemonic#"\t$R1, $XBD2",
[(operator cls:$R1, (load mode:$XBD2))]> {
- let OpKey = mnemonic ## cls;
+ let OpKey = mnemonic#"r"#cls;
let OpType = "mem";
let isCompare = 1;
let mayLoad = 1;
@@ -2861,7 +2888,7 @@ class CompareRXE<string mnemonic, bits<1
: InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
mnemonic#"\t$R1, $XBD2",
[(operator cls:$R1, (load bdxaddr12only:$XBD2))]> {
- let OpKey = mnemonic ## cls;
+ let OpKey = mnemonic#"r"#cls;
let OpType = "mem";
let isCompare = 1;
let mayLoad = 1;
@@ -2875,7 +2902,7 @@ class CompareRXY<string mnemonic, bits<1
: InstRXYa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
mnemonic#"\t$R1, $XBD2",
[(operator cls:$R1, (load mode:$XBD2))]> {
- let OpKey = mnemonic ## cls;
+ let OpKey = mnemonic#"r"#cls;
let OpType = "mem";
let isCompare = 1;
let mayLoad = 1;
@@ -2971,12 +2998,18 @@ class TestRXE<string mnemonic, bits<16>
let M3 = 0;
}
+class TernaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1,
+ RegisterOperand cls2>
+ : InstRRFe<opcode, (outs cls1:$R1),
+ (ins imm32zx4:$M3, cls2:$R2, imm32zx4:$M4),
+ mnemonic#"\t$R1, $M3, $R2, $M4", []>;
+
class TernaryRRD<string mnemonic, bits<16> opcode,
SDPatternOperator operator, RegisterOperand cls>
: InstRRD<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, cls:$R2),
- mnemonic#"r\t$R1, $R3, $R2",
+ mnemonic#"\t$R1, $R3, $R2",
[(set cls:$R1, (operator cls:$R1src, cls:$R3, cls:$R2))]> {
- let OpKey = mnemonic ## cls;
+ let OpKey = mnemonic#cls;
let OpType = "reg";
let Constraints = "$R1 = $R1src";
let DisableEncoding = "$R1src";
@@ -3023,7 +3056,7 @@ class TernaryRXF<string mnemonic, bits<1
mnemonic#"\t$R1, $R3, $XBD2",
[(set cls:$R1, (operator cls:$R1src, cls:$R3,
(load bdxaddr12only:$XBD2)))]> {
- let OpKey = mnemonic ## cls;
+ let OpKey = mnemonic#"r"#cls;
let OpType = "mem";
let Constraints = "$R1 = $R1src";
let DisableEncoding = "$R1src";
@@ -3381,7 +3414,7 @@ class UnaryRXYPseudo<string key, SDPatte
AddressingMode mode = bdxaddr20only>
: Pseudo<(outs cls:$R1), (ins mode:$XBD2),
[(set cls:$R1, (operator mode:$XBD2))]> {
- let OpKey = key ## cls;
+ let OpKey = key#"r"#cls;
let OpType = "mem";
let mayLoad = 1;
let Has20BitOffset = 1;
@@ -3394,7 +3427,7 @@ class UnaryRRPseudo<string key, SDPatter
RegisterOperand cls1, RegisterOperand cls2>
: Pseudo<(outs cls1:$R1), (ins cls2:$R2),
[(set cls1:$R1, (operator cls2:$R2))]> {
- let OpKey = key ## cls1;
+ let OpKey = key#cls1;
let OpType = "reg";
}
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td?rev=286267&r1=286266&r2=286267&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td Tue Nov 8 12:36:31 2016
@@ -328,14 +328,14 @@ defm CondStore64 : CondStores<GR64, nonv
// Register moves.
let hasSideEffects = 0 in {
// Expands to LR, RISBHG or RISBLG, depending on the choice of registers.
- def LRMux : UnaryRRPseudo<"l", null_frag, GRX32, GRX32>,
+ def LRMux : UnaryRRPseudo<"lr", null_frag, GRX32, GRX32>,
Requires<[FeatureHighWord]>;
- def LR : UnaryRR <"l", 0x18, null_frag, GR32, GR32>;
- def LGR : UnaryRRE<"lg", 0xB904, null_frag, GR64, GR64>;
+ def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>;
+ def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>;
}
let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
- def LTR : UnaryRR <"lt", 0x12, null_frag, GR32, GR32>;
- def LTGR : UnaryRRE<"ltg", 0xB902, null_frag, GR64, GR64>;
+ def LTR : UnaryRR <"ltr", 0x12, null_frag, GR32, GR32>;
+ def LTGR : UnaryRRE<"ltgr", 0xB902, null_frag, GR64, GR64>;
}
// Immediate moves.
@@ -479,18 +479,18 @@ let Predicates = [FeatureLoadStoreOnCond
// 32-bit extensions from registers.
let hasSideEffects = 0 in {
- def LBR : UnaryRRE<"lb", 0xB926, sext8, GR32, GR32>;
- def LHR : UnaryRRE<"lh", 0xB927, sext16, GR32, GR32>;
+ def LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>;
+ def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>;
}
// 64-bit extensions from registers.
let hasSideEffects = 0 in {
- def LGBR : UnaryRRE<"lgb", 0xB906, sext8, GR64, GR64>;
- def LGHR : UnaryRRE<"lgh", 0xB907, sext16, GR64, GR64>;
- def LGFR : UnaryRRE<"lgf", 0xB914, sext32, GR64, GR32>;
+ def LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>;
+ def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>;
+ def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>;
}
let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
- def LTGFR : UnaryRRE<"ltgf", 0xB912, null_frag, GR64, GR32>;
+ def LTGFR : UnaryRRE<"ltgfr", 0xB912, null_frag, GR64, GR32>;
// Match 32-to-64-bit sign extensions in which the source is already
// in a 64-bit register.
@@ -530,20 +530,20 @@ let Defs = [CC], CCValues = 0xE, Compare
// 32-bit extensions from registers.
let hasSideEffects = 0 in {
// Expands to LLCR or RISB[LH]G, depending on the choice of registers.
- def LLCRMux : UnaryRRPseudo<"llc", zext8, GRX32, GRX32>,
+ def LLCRMux : UnaryRRPseudo<"llcr", zext8, GRX32, GRX32>,
Requires<[FeatureHighWord]>;
- def LLCR : UnaryRRE<"llc", 0xB994, zext8, GR32, GR32>;
+ def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>;
// Expands to LLHR or RISB[LH]G, depending on the choice of registers.
- def LLHRMux : UnaryRRPseudo<"llh", zext16, GRX32, GRX32>,
+ def LLHRMux : UnaryRRPseudo<"llhr", zext16, GRX32, GRX32>,
Requires<[FeatureHighWord]>;
- def LLHR : UnaryRRE<"llh", 0xB995, zext16, GR32, GR32>;
+ def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>;
}
// 64-bit extensions from registers.
let hasSideEffects = 0 in {
- def LLGCR : UnaryRRE<"llgc", 0xB984, zext8, GR64, GR64>;
- def LLGHR : UnaryRRE<"llgh", 0xB985, zext16, GR64, GR64>;
- def LLGFR : UnaryRRE<"llgf", 0xB916, zext32, GR64, GR32>;
+ def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>;
+ def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>;
+ def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>;
}
// Match 32-to-64-bit zero extensions in which the source is already
@@ -627,8 +627,8 @@ def STMH : StoreMultipleRSY<"stmh", 0xEB
// Byte-swapping register moves.
let hasSideEffects = 0 in {
- def LRVR : UnaryRRE<"lrv", 0xB91F, bswap, GR32, GR32>;
- def LRVGR : UnaryRRE<"lrvg", 0xB90F, bswap, GR64, GR64>;
+ def LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>;
+ def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>;
}
// Byte-swapping loads. Unlike normal loads, these instructions are
@@ -680,11 +680,11 @@ def GOT : Alias<6, (outs GR64:$R1), (ins
let Defs = [CC] in {
let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
- def LPR : UnaryRR <"lp", 0x10, z_iabs, GR32, GR32>;
- def LPGR : UnaryRRE<"lpg", 0xB900, z_iabs, GR64, GR64>;
+ def LPR : UnaryRR <"lpr", 0x10, z_iabs, GR32, GR32>;
+ def LPGR : UnaryRRE<"lpgr", 0xB900, z_iabs, GR64, GR64>;
}
let CCValues = 0xE, CompareZeroCCMask = 0xE in
- def LPGFR : UnaryRRE<"lpgf", 0xB910, null_frag, GR64, GR32>;
+ def LPGFR : UnaryRRE<"lpgfr", 0xB910, null_frag, GR64, GR32>;
}
def : Pat<(z_iabs32 GR32:$src), (LPR GR32:$src)>;
def : Pat<(z_iabs64 GR64:$src), (LPGR GR64:$src)>;
@@ -693,11 +693,11 @@ defm : SXU<z_iabs64, LPGFR>;
let Defs = [CC] in {
let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
- def LNR : UnaryRR <"ln", 0x11, z_inegabs, GR32, GR32>;
- def LNGR : UnaryRRE<"lng", 0xB901, z_inegabs, GR64, GR64>;
+ def LNR : UnaryRR <"lnr", 0x11, z_inegabs, GR32, GR32>;
+ def LNGR : UnaryRRE<"lngr", 0xB901, z_inegabs, GR64, GR64>;
}
let CCValues = 0xE, CompareZeroCCMask = 0xE in
- def LNGFR : UnaryRRE<"lngf", 0xB911, null_frag, GR64, GR32>;
+ def LNGFR : UnaryRRE<"lngfr", 0xB911, null_frag, GR64, GR32>;
}
def : Pat<(z_inegabs32 GR32:$src), (LNR GR32:$src)>;
def : Pat<(z_inegabs64 GR64:$src), (LNGR GR64:$src)>;
@@ -706,11 +706,11 @@ defm : SXU<z_inegabs64, LNGFR>;
let Defs = [CC] in {
let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
- def LCR : UnaryRR <"lc", 0x13, ineg, GR32, GR32>;
- def LCGR : UnaryRRE<"lcg", 0xB903, ineg, GR64, GR64>;
+ def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>;
+ def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>;
}
let CCValues = 0xE, CompareZeroCCMask = 0xE in
- def LCGFR : UnaryRRE<"lcgf", 0xB913, null_frag, GR64, GR32>;
+ def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>;
}
defm : SXU<ineg, LCGFR>;
@@ -778,10 +778,10 @@ def : Pat<(or (zext32 GR32:$src), imm64h
let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in {
// Addition of a register.
let isCommutable = 1 in {
- defm AR : BinaryRRAndK<"a", 0x1A, 0xB9F8, add, GR32, GR32>;
- defm AGR : BinaryRREAndK<"ag", 0xB908, 0xB9E8, add, GR64, GR64>;
+ defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, add, GR32, GR32>;
+ defm AGR : BinaryRREAndK<"agr", 0xB908, 0xB9E8, add, GR64, GR64>;
}
- def AGFR : BinaryRRE<"agf", 0xB918, null_frag, GR64, GR32>;
+ def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>;
// Addition of signed 16-bit immediates.
defm AHIMux : BinaryRIAndKPseudo<"ahimux", add, GRX32, imm32sx16>;
@@ -812,10 +812,10 @@ defm : SXB<add, GR64, AGFR>;
let Defs = [CC] in {
// Addition of a register.
let isCommutable = 1 in {
- defm ALR : BinaryRRAndK<"al", 0x1E, 0xB9FA, addc, GR32, GR32>;
- defm ALGR : BinaryRREAndK<"alg", 0xB90A, 0xB9EA, addc, GR64, GR64>;
+ defm ALR : BinaryRRAndK<"alr", 0x1E, 0xB9FA, addc, GR32, GR32>;
+ defm ALGR : BinaryRREAndK<"algr", 0xB90A, 0xB9EA, addc, GR64, GR64>;
}
- def ALGFR : BinaryRRE<"algf", 0xB91A, null_frag, GR64, GR32>;
+ def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>;
// Addition of signed 16-bit immediates.
def ALHSIK : BinaryRIE<"alhsik", 0xECDA, addc, GR32, imm32sx16>,
@@ -837,8 +837,8 @@ defm : ZXB<addc, GR64, ALGFR>;
// Addition producing and using a carry.
let Defs = [CC], Uses = [CC] in {
// Addition of a register.
- def ALCR : BinaryRRE<"alc", 0xB998, adde, GR32, GR32>;
- def ALCGR : BinaryRRE<"alcg", 0xB988, adde, GR64, GR64>;
+ def ALCR : BinaryRRE<"alcr", 0xB998, adde, GR32, GR32>;
+ def ALCGR : BinaryRRE<"alcgr", 0xB988, adde, GR64, GR64>;
// Addition of memory.
def ALC : BinaryRXY<"alc", 0xE398, adde, GR32, load, 4>;
@@ -853,9 +853,9 @@ let Defs = [CC], Uses = [CC] in {
// add-immediate instruction instead.
let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in {
// Subtraction of a register.
- defm SR : BinaryRRAndK<"s", 0x1B, 0xB9F9, sub, GR32, GR32>;
- def SGFR : BinaryRRE<"sgf", 0xB919, null_frag, GR64, GR32>;
- defm SGR : BinaryRREAndK<"sg", 0xB909, 0xB9E9, sub, GR64, GR64>;
+ defm SR : BinaryRRAndK<"sr", 0x1B, 0xB9F9, sub, GR32, GR32>;
+ def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>;
+ defm SGR : BinaryRREAndK<"sgr", 0xB909, 0xB9E9, sub, GR64, GR64>;
// Subtraction of memory.
defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, asextloadi16, 2>;
@@ -868,9 +868,9 @@ defm : SXB<sub, GR64, SGFR>;
// Subtraction producing a carry.
let Defs = [CC] in {
// Subtraction of a register.
- defm SLR : BinaryRRAndK<"sl", 0x1F, 0xB9FB, subc, GR32, GR32>;
- def SLGFR : BinaryRRE<"slgf", 0xB91B, null_frag, GR64, GR32>;
- defm SLGR : BinaryRREAndK<"slg", 0xB90B, 0xB9EB, subc, GR64, GR64>;
+ defm SLR : BinaryRRAndK<"slr", 0x1F, 0xB9FB, subc, GR32, GR32>;
+ def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>;
+ defm SLGR : BinaryRREAndK<"slgr", 0xB90B, 0xB9EB, subc, GR64, GR64>;
// Subtraction of unsigned 32-bit immediates. These don't match
// subc because we prefer addc for constants.
@@ -887,8 +887,8 @@ defm : ZXB<subc, GR64, SLGFR>;
// Subtraction producing and using a carry.
let Defs = [CC], Uses = [CC] in {
// Subtraction of a register.
- def SLBR : BinaryRRE<"slb", 0xB999, sube, GR32, GR32>;
- def SLBGR : BinaryRRE<"slbg", 0xB989, sube, GR64, GR64>;
+ def SLBR : BinaryRRE<"slbr", 0xB999, sube, GR32, GR32>;
+ def SLBGR : BinaryRRE<"slbgr", 0xB989, sube, GR64, GR64>;
// Subtraction of memory.
def SLB : BinaryRXY<"slb", 0xE399, sube, GR32, load, 4>;
@@ -902,8 +902,8 @@ let Defs = [CC], Uses = [CC] in {
let Defs = [CC] in {
// ANDs of a register.
let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
- defm NR : BinaryRRAndK<"n", 0x14, 0xB9F4, and, GR32, GR32>;
- defm NGR : BinaryRREAndK<"ng", 0xB980, 0xB9E4, and, GR64, GR64>;
+ defm NR : BinaryRRAndK<"nr", 0x14, 0xB9F4, and, GR32, GR32>;
+ defm NGR : BinaryRREAndK<"ngr", 0xB980, 0xB9E4, and, GR64, GR64>;
}
let isConvertibleToThreeAddress = 1 in {
@@ -961,8 +961,8 @@ defm : RMWIByte<and, bdaddr20pair, NIY>;
let Defs = [CC] in {
// ORs of a register.
let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
- defm OR : BinaryRRAndK<"o", 0x16, 0xB9F6, or, GR32, GR32>;
- defm OGR : BinaryRREAndK<"og", 0xB981, 0xB9E6, or, GR64, GR64>;
+ defm OR : BinaryRRAndK<"or", 0x16, 0xB9F6, or, GR32, GR32>;
+ defm OGR : BinaryRREAndK<"ogr", 0xB981, 0xB9E6, or, GR64, GR64>;
}
// ORs of a 16-bit immediate, leaving other bits unaffected.
@@ -1018,8 +1018,8 @@ defm : RMWIByte<or, bdaddr20pair, OIY>;
let Defs = [CC] in {
// XORs of a register.
let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
- defm XR : BinaryRRAndK<"x", 0x17, 0xB9F7, xor, GR32, GR32>;
- defm XGR : BinaryRREAndK<"xg", 0xB982, 0xB9E7, xor, GR64, GR64>;
+ defm XR : BinaryRRAndK<"xr", 0x17, 0xB9F7, xor, GR32, GR32>;
+ defm XGR : BinaryRREAndK<"xgr", 0xB982, 0xB9E7, xor, GR64, GR64>;
}
// XORs of a 32-bit immediate, leaving other bits unaffected.
@@ -1057,10 +1057,10 @@ defm : RMWIByte<xor, bdaddr20pair, XIY>;
// Multiplication of a register.
let isCommutable = 1 in {
- def MSR : BinaryRRE<"ms", 0xB252, mul, GR32, GR32>;
- def MSGR : BinaryRRE<"msg", 0xB90C, mul, GR64, GR64>;
+ def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>;
+ def MSGR : BinaryRRE<"msgr", 0xB90C, mul, GR64, GR64>;
}
-def MSGFR : BinaryRRE<"msgf", 0xB91C, null_frag, GR64, GR32>;
+def MSGFR : BinaryRRE<"msgfr", 0xB91C, null_frag, GR64, GR32>;
defm : SXB<mul, GR64, MSGFR>;
// Multiplication of a signed 16-bit immediate.
@@ -1078,7 +1078,7 @@ def MSGF : BinaryRXY<"msgf", 0xE31C, mu
def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>;
// Multiplication of a register, producing two results.
-def MLGR : BinaryRRE<"mlg", 0xB986, z_umul_lohi64, GR128, GR64>;
+def MLGR : BinaryRRE<"mlgr", 0xB986, z_umul_lohi64, GR128, GR64>;
// Multiplication of memory, producing two results.
def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load, 8>;
@@ -1088,10 +1088,10 @@ def MLG : BinaryRXY<"mlg", 0xE386, z_umu
//===----------------------------------------------------------------------===//
// Division and remainder, from registers.
-def DSGFR : BinaryRRE<"dsgf", 0xB91D, z_sdivrem32, GR128, GR32>;
-def DSGR : BinaryRRE<"dsg", 0xB90D, z_sdivrem64, GR128, GR64>;
-def DLR : BinaryRRE<"dl", 0xB997, z_udivrem32, GR128, GR32>;
-def DLGR : BinaryRRE<"dlg", 0xB987, z_udivrem64, GR128, GR64>;
+def DSGFR : BinaryRRE<"dsgfr", 0xB91D, z_sdivrem32, GR128, GR32>;
+def DSGR : BinaryRRE<"dsgr", 0xB90D, z_sdivrem64, GR128, GR64>;
+def DLR : BinaryRRE<"dlr", 0xB997, z_udivrem32, GR128, GR32>;
+def DLGR : BinaryRRE<"dlgr", 0xB987, z_udivrem64, GR128, GR64>;
// Division and remainder, from memory.
def DSGF : BinaryRXY<"dsgf", 0xE31D, z_sdivrem32, GR128, load, 4>;
@@ -1172,9 +1172,9 @@ let Defs = [CC] in {
// of the unsigned forms do.
let Defs = [CC], CCValues = 0xE in {
// Comparison with a register.
- def CR : CompareRR <"c", 0x19, z_scmp, GR32, GR32>;
- def CGFR : CompareRRE<"cgf", 0xB930, null_frag, GR64, GR32>;
- def CGR : CompareRRE<"cg", 0xB920, z_scmp, GR64, GR64>;
+ def CR : CompareRR <"cr", 0x19, z_scmp, GR32, GR32>;
+ def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>;
+ def CGR : CompareRRE<"cgr", 0xB920, z_scmp, GR64, GR64>;
// Comparison with a signed 16-bit immediate.
def CHI : CompareRI<"chi", 0xA7E, z_scmp, GR32, imm32sx16>;
@@ -1215,9 +1215,9 @@ defm : SXB<z_scmp, GR64, CGFR>;
// Unsigned comparisons.
let Defs = [CC], CCValues = 0xE, IsLogical = 1 in {
// Comparison with a register.
- def CLR : CompareRR <"cl", 0x15, z_ucmp, GR32, GR32>;
- def CLGFR : CompareRRE<"clgf", 0xB931, null_frag, GR64, GR32>;
- def CLGR : CompareRRE<"clg", 0xB921, z_ucmp, GR64, GR64>;
+ def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>;
+ def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>;
+ def CLGR : CompareRRE<"clgr", 0xB921, z_ucmp, GR64, GR64>;
// Comparison with an unsigned 32-bit immediate. CLFIMux expands to CLFI
// or CLIH, depending on the choice of register.
@@ -1495,9 +1495,9 @@ let Predicates = [FeatureTransactionalEx
//===----------------------------------------------------------------------===//
let Predicates = [FeatureProcessorAssist] in {
- let hasSideEffects = 1, R4 = 0 in
- def PPA : InstRRF<0xB2E8, (outs), (ins GR64:$R1, GR64:$R2, imm32zx4:$R3),
- "ppa\t$R1, $R2, $R3", []>;
+ let hasSideEffects = 1 in
+ def PPA : InstRRFc<0xB2E8, (outs), (ins GR64:$R1, GR64:$R2, imm32zx4:$M3),
+ "ppa\t$R1, $R2, $M3", []>;
def : Pat<(int_s390_ppa_txassist GR32:$src),
(PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32),
0, 1)>;
@@ -1523,7 +1523,7 @@ def EAR : InstRRE<0xB24F, (outs GR32:$R1
// and the second giving a copy of the source with the leftmost one bit
// cleared. We only use the first result here.
let Defs = [CC] in {
- def FLOGR : UnaryRRE<"flog", 0xB983, null_frag, GR128, GR64>;
+ def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>;
}
def : Pat<(ctlz GR64:$src),
(EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>;
@@ -1630,8 +1630,8 @@ let isCodeGenOnly = 1 in {
".insn rre,$enc,$R1,$R2", []>;
def InsnRRF : DirectiveInsnRRF<(outs),
(ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2,
- AnyReg:$R3, imm32zx4:$R4),
- ".insn rrf,$enc,$R1,$R2,$R3,$R4", []>;
+ AnyReg:$R3, imm32zx4:$M4),
+ ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>;
def InsnRRS : DirectiveInsnRRS<(outs),
(ins imm64zx48:$enc, AnyReg:$R1,
AnyReg:$R2, imm32zx4:$M3,
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