[PATCH] D26400: AMDGPU: Set hasExtraSrcRegAllocReq on v_div_scale_*

[Matt Arsenault via llvm-commits]

arsenm created this revision.
arsenm added a subscriber: llvm-commits.
Herald added a reviewer: tstellarAMD.
Herald added subscribers: tony-tye, yaxunl, nhaehnle, wdng, kzhuravl.

This doesn't solve any problems I know about, but this should have more conservative assumptions about the operands


https://reviews.llvm.org/D26400

Files:
  lib/Target/AMDGPU/SIInstructions.td


Index: lib/Target/AMDGPU/SIInstructions.td
===================================================================
--- lib/Target/AMDGPU/SIInstructions.td
+++ lib/Target/AMDGPU/SIInstructions.td
@@ -1831,7 +1831,7 @@
 
 } // End isCommutable = 1, SchedRW = [WriteQuarterRate32]
 
-let SchedRW = [WriteFloatFMA, WriteSALU] in {
+let SchedRW = [WriteFloatFMA, WriteSALU], hasExtraSrcRegAllocReq = 1 in {
 defm V_DIV_SCALE_F32 : VOP3bInst <vop3<0x16d, 0x1e0>, "v_div_scale_f32",
   VOP3b_F32_I1_F32_F32_F32, [], 1
 >;


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