[PATCH] D26313: [AArch64] Transfer memory operands when lowering vector load and store intrinsics

[Sanjin Sijaric via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL286168: [AArch64] Transfer memory operands when lowering vector load/store intrinsics (authored by ssijaric).

Changed prior to commit:
  https://reviews.llvm.org/D26313?vs=76948&id=77104#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D26313

Files:
  llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/trunk/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
  llvm/trunk/test/CodeGen/AArch64/sched-past-vector-ldst.ll

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