[PATCH] D25551: AMDGPU: Implement SGPR spilling with scalar stores

[Matt Arsenault via llvm-commits]

arsenm added inline comments.


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Comment at: test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll:27-37
+; SMEM: s_mov_b32 m0, s97{{$}}
+; SMEM: s_buffer_load_dword s{{[0-9]+}}, s[92:95], m0 ; 16-byte Folded Reload
+; SMEM: s_add_u32 m0, s97, 0x100{{$}}
+; SMEM: s_waitcnt lgkmcnt(0)
+; SMEM: s_buffer_load_dword s{{[0-9]+}}, s[92:95], m0 ; 16-byte Folded Reload
+; SMEM: s_add_u32 m0, s97, 0x200{{$}}
+; SMEM: s_waitcnt lgkmcnt(0)
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nhaehnle wrote:
> I'm a bit surprised by the offsets as they seem too far apart. I guess the offset allocation assumes VGPR spilling, and this is a TODO to be fixed later? Should probably be mentioned here in the test and in the appropriate location in the code.
The offsets need to be multiplied by the wave size, so they end up looking big. It would be a code size improvement to use the previous one when splitting the spill (although this is mitigated by using the wider instructions in the follow up patch)


https://reviews.llvm.org/D25551