[llvm] r286049 - [Hexagon] Relocate pattern-related bits to proper places
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Sat Nov 5 14:44:51 PDT 2016
Author: kparzysz
Date: Sat Nov 5 16:44:50 2016
New Revision: 286049
URL: http://llvm.org/viewvc/llvm-project?rev=286049&view=rev
Log:
[Hexagon] Relocate pattern-related bits to proper places
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h
llvm/trunk/lib/Target/Hexagon/HexagonOperands.td
llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td
llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp?rev=286049&r1=286048&r2=286049&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp Sat Nov 5 16:44:50 2016
@@ -186,6 +186,7 @@ private:
bool isValueExtension(const SDValue &Val, unsigned FromBits, SDValue &Src);
bool orIsAdd(const SDNode *N) const;
bool isAlignedMemNode(const MemSDNode *N) const;
+ bool isPositiveHalfWord(const SDNode *N) const;
SmallDenseMap<SDNode *,int> RootWeights;
SmallDenseMap<SDNode *,int> RootHeights;
@@ -1538,6 +1539,19 @@ bool HexagonDAGToDAGISel::isAlignedMemNo
return N->getAlignment() >= N->getMemoryVT().getStoreSize();
}
+// Return true when the given node fits in a positive half word.
+bool HexagonDAGToDAGISel::isPositiveHalfWord(const SDNode *N) const {
+ if (const ConstantSDNode *CN = dyn_cast<const ConstantSDNode>(N)) {
+ int64_t V = CN->getSExtValue();
+ return V > 0 && isInt<16>(V);
+ }
+ if (N->getOpcode() == ISD::SIGN_EXTEND_INREG) {
+ const VTSDNode *VN = dyn_cast<const VTSDNode>(N->getOperand(1));
+ return VN->getVT().getSizeInBits() <= 16;
+ }
+ return false;
+}
+
////////////////////////////////////////////////////////////////////////////////
// Rebalancing of address calculation trees
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=286049&r1=286048&r2=286049&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Sat Nov 5 16:44:50 2016
@@ -3201,20 +3201,6 @@ EVT HexagonTargetLowering::getOptimalMem
return MVT::Other;
}
-// Return true when the given node fits in a positive half word.
-bool llvm::isPositiveHalfWord(SDNode *N) {
- ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
- if (CN && CN->getSExtValue() > 0 && isInt<16>(CN->getSExtValue()))
- return true;
-
- switch (N->getOpcode()) {
- default:
- return false;
- case ISD::SIGN_EXTEND_INREG:
- return true;
- }
-}
-
bool HexagonTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
unsigned AS, unsigned Align, bool *Fast) const {
if (Fast)
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h?rev=286049&r1=286048&r2=286049&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h Sat Nov 5 16:44:50 2016
@@ -21,10 +21,6 @@
#include "llvm/Target/TargetLowering.h"
namespace llvm {
-
-// Return true when the given node fits in a positive half word.
-bool isPositiveHalfWord(SDNode *N);
-
namespace HexagonISD {
enum NodeType : unsigned {
OP_BEGIN = ISD::BUILTIN_OP_END,
Modified: llvm/trunk/lib/Target/Hexagon/HexagonOperands.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonOperands.td?rev=286049&r1=286048&r2=286049&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonOperands.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonOperands.td Sat Nov 5 16:44:50 2016
@@ -258,25 +258,6 @@ def nOneImmPred : PatLeaf<(i32 imm), [{
return (-1 == v);
}]>;
-def Set5ImmPred : PatLeaf<(i32 imm), [{
- // Set5ImmPred predicate - True if the number is in the series of values.
- // [ 2^0, 2^1, ... 2^31 ]
- // For use in setbit immediate.
- uint32_t v = (int32_t)N->getSExtValue();
- // Constrain to 32 bits, and then check for single bit.
- return ImmIsSingleBit(v);
-}]>;
-
-def Clr5ImmPred : PatLeaf<(i32 imm), [{
- // Clr5ImmPred predicate - True if the number is in the series of
- // bit negated values.
- // [ 2^0, 2^1, ... 2^31 ]
- // For use in clrbit immediate.
- // Note: we are bit NOTing the value.
- uint32_t v = ~ (int32_t)N->getSExtValue();
- // Constrain to 32 bits, and then check for single bit.
- return ImmIsSingleBit(v);
-}]>;
// Extendable immediate operands.
def f32ExtOperand : AsmOperandClass { let Name = "f32Ext"; }
@@ -394,12 +375,3 @@ def calltarget : Operand<i32> {
def bblabel : Operand<i32>;
def bbl : SDNode<"ISD::BasicBlock", SDTPtrLeaf, [], "BasicBlockSDNode">;
-
-// Return true if for a 32 to 64-bit sign-extended load.
-def is_sext_i32 : PatLeaf<(i64 DoubleRegs:$src1), [{
- LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
- if (!LD)
- return false;
- return LD->getExtensionType() == ISD::SEXTLOAD &&
- LD->getMemoryVT().getScalarType() == MVT::i32;
-}]>;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td?rev=286049&r1=286048&r2=286049&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td Sat Nov 5 16:44:50 2016
@@ -19,6 +19,26 @@ def HiReg: OutPatFrag<(ops node:$Rs),
def orisadd: PatFrag<(ops node:$Addr, node:$off),
(or node:$Addr, node:$off), [{ return orIsAdd(N); }]>;
+def Set5ImmPred : PatLeaf<(i32 imm), [{
+ // Set5ImmPred predicate - True if the number is in the series of values.
+ // [ 2^0, 2^1, ... 2^31 ]
+ // For use in setbit immediate.
+ uint32_t v = N->getZExtValue();
+ // Constrain to 32 bits, and then check for single bit.
+ return isPowerOf2_32(v);
+}]>;
+
+def Clr5ImmPred : PatLeaf<(i32 imm), [{
+ // Clr5ImmPred predicate - True if the number is in the series of
+ // bit negated values.
+ // [ 2^0, 2^1, ... 2^31 ]
+ // For use in clrbit immediate.
+ // Note: we are bit NOTing the value.
+ uint32_t v = ~N->getZExtValue();
+ // Constrain to 32 bits, and then check for single bit.
+ return isPowerOf2_32(v);
+}]>;
+
// SDNode for converting immediate C to C-1.
def DEC_CONST_SIGNED : SDNodeXForm<imm, [{
// Return the byte immediate const-1 as an SDNode.
@@ -175,6 +195,9 @@ multiclass T_MinMax_pats <PatFrag Op, Re
(SwapInst RC:$src1, RC:$src2)>;
}
+def PositiveHalfWord : PatLeaf<(i32 IntRegs:$a), [{
+ return isPositiveHalfWord(N);
+}]>;
multiclass MinMax_pats <PatFrag Op, InstHexagon Inst, InstHexagon SwapInst> {
defm: T_MinMax_pats<Op, IntRegs, i32, Inst, SwapInst>;
@@ -336,16 +359,24 @@ def: T_MType_acc_pat3 <M4_or_andn, and,
def: T_MType_acc_pat3 <M4_and_andn, and, and>;
def: T_MType_acc_pat3 <M4_xor_andn, and, xor>;
-def: Pat<(i64 (mul (i64 (anyext (i32 IntRegs:$src1))),
- (i64 (anyext (i32 IntRegs:$src2))))),
+// Return true if for a 32 to 64-bit sign-extended load.
+def Sext64Ld : PatLeaf<(i64 DoubleRegs:$src1), [{
+ LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
+ if (!LD)
+ return false;
+ return LD->getExtensionType() == ISD::SEXTLOAD &&
+ LD->getMemoryVT().getScalarType() == MVT::i32;
+}]>;
+
+def: Pat<(i64 (mul (i64 (anyext I32:$src1)),
+ (i64 (anyext I32:$src2)))),
(M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2)>;
-def: Pat<(i64 (mul (i64 (sext (i32 IntRegs:$src1))),
- (i64 (sext (i32 IntRegs:$src2))))),
+def: Pat<(i64 (mul (i64 (sext I32:$src1)),
+ (i64 (sext I32:$src2)))),
(M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2)>;
-def: Pat<(i64 (mul (is_sext_i32:$src1),
- (is_sext_i32:$src2))),
+def: Pat<(i64 (mul Sext64Ld:$src1, Sext64Ld:$src2)),
(M2_dpmpyss_s0 (LoReg DoubleRegs:$src1), (LoReg DoubleRegs:$src2))>;
// Multiply and accumulate, use full result.
Modified: llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td?rev=286049&r1=286048&r2=286049&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td Sat Nov 5 16:44:50 2016
@@ -282,8 +282,3 @@ def VolatileV3 {
W12, W13, W14, W15,
Q0, Q1, Q2, Q3];
}
-
-def PositiveHalfWord : PatLeaf<(i32 IntRegs:$a),
-[{
- return isPositiveHalfWord(N);
-}]>;
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