[PATCH] D26120: [Cortex-M0] Atomic lowering

[Weiming Zhao via llvm-commits]

weimingz added inline comments.


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Comment at: lib/Target/ARM/ARMISelLowering.cpp:12880
   unsigned Size = AI->getType()->getPrimitiveSizeInBits();
-  return (Size <= (Subtarget->isMClass() ? 32U : 64U))
+  bool hasAtomicRMW = !Subtarget->isThumb() || Subtarget->hasV8MBaselineOps();
+  return (Size <= (Subtarget->isMClass() ? 32U : 64U) && hasAtomicRMW)
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jmolloy wrote:
> What about ARMv7-A/R here? Previously we'd return LLSC in this case.
ARMv7-A/R should not be affected because they have V8MBaselineOps() (inherits from v6t2)


Repository:
  rL LLVM

https://reviews.llvm.org/D26120