[llvm] r285866 - Revert "[InstCombine] allow splat vector folds in adjustMinMax()"
Greg Bedwell via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 2 16:17:05 PDT 2016
Author: gbedwell
Date: Wed Nov 2 18:17:05 2016
New Revision: 285866
URL: http://llvm.org/viewvc/llvm-project?rev=285866&view=rev
Log:
Revert "[InstCombine] allow splat vector folds in adjustMinMax()"
This reverts commit r285732.
This change introduced a new assertion failure in the following
testcase at -O2:
typedef short __v8hi __attribute__((__vector_size__(16)));
__v8hi foo(__v8hi &V1, __v8hi &V2, unsigned mask) {
__v8hi Result = V1;
if (mask & 0x80)
Result[0] = V2[0];
return Result;
}
Modified:
llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp
llvm/trunk/test/Transforms/InstCombine/adjust-for-minmax.ll
Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp?rev=285866&r1=285865&r2=285866&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Wed Nov 2 18:17:05 2016
@@ -424,20 +424,24 @@ static bool adjustMinMax(SelectInst &Sel
Value *FalseVal = Sel.getFalseValue();
// We may move or edit the compare, so make sure the select is the only user.
- const APInt *CmpC;
- if (!Cmp.hasOneUse() || !match(CmpRHS, m_APInt(CmpC)))
+ if (!Cmp.hasOneUse())
return false;
- // These transforms only work for selects of integers or vector integers.
- auto *SelEltTy = dyn_cast<IntegerType>(Sel.getType()->getScalarType());
- if (!SelEltTy)
+ // FIXME: Use m_APInt to allow vector folds.
+ auto *CI = dyn_cast<ConstantInt>(CmpRHS);
+ if (!CI)
+ return false;
+
+ // These transformations only work for selects over integers.
+ IntegerType *SelectTy = dyn_cast<IntegerType>(Sel.getType());
+ if (!SelectTy)
return false;
Constant *AdjustedRHS;
if (Pred == ICmpInst::ICMP_UGT || Pred == ICmpInst::ICMP_SGT)
- AdjustedRHS = ConstantInt::get(CmpRHS->getType(), *CmpC + 1);
+ AdjustedRHS = ConstantInt::get(CI->getContext(), CI->getValue() + 1);
else if (Pred == ICmpInst::ICMP_ULT || Pred == ICmpInst::ICMP_SLT)
- AdjustedRHS = ConstantInt::get(CmpRHS->getType(), *CmpC - 1);
+ AdjustedRHS = ConstantInt::get(CI->getContext(), CI->getValue() - 1);
else
return false;
@@ -450,8 +454,8 @@ static bool adjustMinMax(SelectInst &Sel
// Types do not match. Instead of calculating this with mixed types, promote
// all to the larger type. This enables scalar evolution to analyze this
// expression.
- else if (CmpRHS->getType()->getScalarSizeInBits() < SelEltTy->getBitWidth()) {
- Constant *SextRHS = ConstantExpr::getSExt(AdjustedRHS, Sel.getType());
+ else if (CmpRHS->getType()->getScalarSizeInBits() < SelectTy->getBitWidth()) {
+ Constant *SextRHS = ConstantExpr::getSExt(AdjustedRHS, SelectTy);
// X = sext x; x >s c ? X : C+1 --> X = sext x; X <s C+1 ? C+1 : X
// X = sext x; x <s c ? X : C-1 --> X = sext x; X >s C-1 ? C-1 : X
@@ -465,7 +469,7 @@ static bool adjustMinMax(SelectInst &Sel
CmpLHS = FalseVal;
AdjustedRHS = SextRHS;
} else if (Cmp.isUnsigned()) {
- Constant *ZextRHS = ConstantExpr::getZExt(AdjustedRHS, Sel.getType());
+ Constant *ZextRHS = ConstantExpr::getZExt(AdjustedRHS, SelectTy);
// X = zext x; x >u c ? X : C+1 --> X = zext x; X <u C+1 ? C+1 : X
// X = zext x; x <u c ? X : C-1 --> X = zext x; X >u C-1 ? C-1 : X
// zext + signed compare cannot be changed:
Modified: llvm/trunk/test/Transforms/InstCombine/adjust-for-minmax.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/adjust-for-minmax.ll?rev=285866&r1=285865&r2=285866&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/adjust-for-minmax.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/adjust-for-minmax.ll Wed Nov 2 18:17:05 2016
@@ -68,12 +68,13 @@ define i32 @smax3(i32 %n) {
ret i32 %m
}
+; FIXME
; Swap vector signed pred and select ops.
define <2 x i32> @smax3_vec(<2 x i32> %n) {
; CHECK-LABEL: @smax3_vec(
-; CHECK-NEXT: [[T:%.*]] = icmp slt <2 x i32> %n, zeroinitializer
-; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> zeroinitializer, <2 x i32> %n
+; CHECK-NEXT: [[T:%.*]] = icmp sgt <2 x i32> %n, <i32 -1, i32 -1>
+; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> zeroinitializer
; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp sgt <2 x i32> %n, <i32 -1, i32 -1>
@@ -94,12 +95,13 @@ define i32 @smin3(i32 %n) {
ret i32 %m
}
+; FIXME
; Swap vector signed pred and select ops.
define <2 x i32> @smin3_vec(<2 x i32> %n) {
; CHECK-LABEL: @smin3_vec(
-; CHECK-NEXT: [[T:%.*]] = icmp sgt <2 x i32> %n, zeroinitializer
-; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> zeroinitializer, <2 x i32> %n
+; CHECK-NEXT: [[T:%.*]] = icmp slt <2 x i32> %n, <i32 1, i32 1>
+; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> zeroinitializer
; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp slt <2 x i32> %n, <i32 1, i32 1>
@@ -120,12 +122,13 @@ define i32 @umax3(i32 %n) {
ret i32 %m
}
+; FIXME
; Swap vector unsigned pred and select ops.
define <2 x i32> @umax3_vec(<2 x i32> %n) {
; CHECK-LABEL: @umax3_vec(
-; CHECK-NEXT: [[T:%.*]] = icmp ult <2 x i32> %n, <i32 5, i32 5>
-; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> <i32 5, i32 5>, <2 x i32> %n
+; CHECK-NEXT: [[T:%.*]] = icmp ugt <2 x i32> %n, <i32 4, i32 4>
+; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> <i32 5, i32 5>
; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp ugt <2 x i32> %n, <i32 4, i32 4>
@@ -146,12 +149,13 @@ define i32 @umin3(i32 %n) {
ret i32 %m
}
+; FIXME
; Swap vector unsigned pred and select ops.
define <2 x i32> @umin3_vec(<2 x i32> %n) {
; CHECK-LABEL: @umin3_vec(
-; CHECK-NEXT: [[T:%.*]] = icmp ugt <2 x i32> %n, <i32 6, i32 6>
-; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> <i32 6, i32 6>, <2 x i32> %n
+; CHECK-NEXT: [[T:%.*]] = icmp ult <2 x i32> %n, <i32 7, i32 7>
+; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> <i32 6, i32 6>
; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp ult <2 x i32> %n, <i32 7, i32 7>
@@ -172,12 +176,13 @@ define i32 @smax4(i32 %n) {
ret i32 %m
}
+; FIXME
; Canonicalize vector signed pred and swap pred and select ops.
define <2 x i32> @smax4_vec(<2 x i32> %n) {
; CHECK-LABEL: @smax4_vec(
-; CHECK-NEXT: [[T:%.*]] = icmp slt <2 x i32> %n, zeroinitializer
-; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> zeroinitializer, <2 x i32> %n
+; CHECK-NEXT: [[T:%.*]] = icmp sgt <2 x i32> %n, <i32 -1, i32 -1>
+; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> zeroinitializer
; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp sge <2 x i32> %n, zeroinitializer
@@ -198,12 +203,13 @@ define i32 @smin4(i32 %n) {
ret i32 %m
}
+; FIXME
; Canonicalize vector signed pred and swap pred and select ops.
define <2 x i32> @smin4_vec(<2 x i32> %n) {
; CHECK-LABEL: @smin4_vec(
-; CHECK-NEXT: [[T:%.*]] = icmp sgt <2 x i32> %n, zeroinitializer
-; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> zeroinitializer, <2 x i32> %n
+; CHECK-NEXT: [[T:%.*]] = icmp slt <2 x i32> %n, <i32 1, i32 1>
+; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> zeroinitializer
; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp sle <2 x i32> %n, zeroinitializer
@@ -224,12 +230,13 @@ define i32 @umax4(i32 %n) {
ret i32 %m
}
+; FIXME
; Canonicalize vector unsigned pred and swap pred and select ops.
define <2 x i32> @umax4_vec(<2 x i32> %n) {
; CHECK-LABEL: @umax4_vec(
-; CHECK-NEXT: [[T:%.*]] = icmp ult <2 x i32> %n, <i32 8, i32 8>
-; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> <i32 8, i32 8>, <2 x i32> %n
+; CHECK-NEXT: [[T:%.*]] = icmp ugt <2 x i32> %n, <i32 7, i32 7>
+; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> <i32 8, i32 8>
; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp uge <2 x i32> %n, <i32 8, i32 8>
@@ -250,12 +257,13 @@ define i32 @umin4(i32 %n) {
ret i32 %m
}
+; FIXME
; Canonicalize vector unsigned pred and swap pred and select ops.
define <2 x i32> @umin4_vec(<2 x i32> %n) {
; CHECK-LABEL: @umin4_vec(
-; CHECK-NEXT: [[T:%.*]] = icmp ugt <2 x i32> %n, <i32 9, i32 9>
-; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> <i32 9, i32 9>, <2 x i32> %n
+; CHECK-NEXT: [[T:%.*]] = icmp ult <2 x i32> %n, <i32 10, i32 10>
+; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> <i32 9, i32 9>
; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp ule <2 x i32> %n, <i32 9, i32 9>
@@ -276,11 +284,12 @@ define i64 @smax_sext(i32 %a) {
ret i64 %max
}
+; FIXME
define <2 x i64> @smax_sext_vec(<2 x i32> %a) {
; CHECK-LABEL: @smax_sext_vec(
; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> %a to <2 x i64>
-; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i64> [[A_EXT]], zeroinitializer
-; CHECK-NEXT: [[MAX:%.*]] = select <2 x i1> [[CMP]], <2 x i64> zeroinitializer, <2 x i64> [[A_EXT]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> %a, <i32 -1, i32 -1>
+; CHECK-NEXT: [[MAX:%.*]] = select <2 x i1> [[CMP]], <2 x i64> [[A_EXT]], <2 x i64> zeroinitializer
; CHECK-NEXT: ret <2 x i64> [[MAX]]
;
%a_ext = sext <2 x i32> %a to <2 x i64>
@@ -302,11 +311,12 @@ define i64 @smin_sext(i32 %a) {
ret i64 %min
}
+; FIXME
define <2 x i64>@smin_sext_vec(<2 x i32> %a) {
; CHECK-LABEL: @smin_sext_vec(
; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> %a to <2 x i64>
-; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i64> [[A_EXT]], zeroinitializer
-; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> zeroinitializer, <2 x i64> [[A_EXT]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> %a, <i32 1, i32 1>
+; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> [[A_EXT]], <2 x i64> zeroinitializer
; CHECK-NEXT: ret <2 x i64> [[MIN]]
;
%a_ext = sext <2 x i32> %a to <2 x i64>
@@ -328,11 +338,12 @@ define i64 @umax_sext(i32 %a) {
ret i64 %max
}
+; FIXME
define <2 x i64> @umax_sext_vec(<2 x i32> %a) {
; CHECK-LABEL: @umax_sext_vec(
; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> %a to <2 x i64>
-; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i64> [[A_EXT]], <i64 3, i64 3>
-; CHECK-NEXT: [[MAX:%.*]] = select <2 x i1> [[CMP]], <2 x i64> <i64 3, i64 3>, <2 x i64> [[A_EXT]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> %a, <i32 2, i32 2>
+; CHECK-NEXT: [[MAX:%.*]] = select <2 x i1> [[CMP]], <2 x i64> [[A_EXT]], <2 x i64> <i64 3, i64 3>
; CHECK-NEXT: ret <2 x i64> [[MAX]]
;
%a_ext = sext <2 x i32> %a to <2 x i64>
@@ -354,11 +365,12 @@ define i64 @umin_sext(i32 %a) {
ret i64 %min
}
+; FIXME
define <2 x i64> @umin_sext_vec(<2 x i32> %a) {
; CHECK-LABEL: @umin_sext_vec(
; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> %a to <2 x i64>
-; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i64> [[A_EXT]], <i64 2, i64 2>
-; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> <i64 2, i64 2>, <2 x i64> [[A_EXT]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> %a, <i32 3, i32 3>
+; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> [[A_EXT]], <2 x i64> <i64 2, i64 2>
; CHECK-NEXT: ret <2 x i64> [[MIN]]
;
%a_ext = sext <2 x i32> %a to <2 x i64>
@@ -380,11 +392,12 @@ define i64 @umax_sext2(i32 %a) {
ret i64 %min
}
+; FIXME
define <2 x i64> @umax_sext2_vec(<2 x i32> %a) {
; CHECK-LABEL: @umax_sext2_vec(
; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> %a to <2 x i64>
-; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i64> [[A_EXT]], <i64 2, i64 2>
-; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> [[A_EXT]], <2 x i64> <i64 2, i64 2>
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> %a, <i32 3, i32 3>
+; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> <i64 2, i64 2>, <2 x i64> [[A_EXT]]
; CHECK-NEXT: ret <2 x i64> [[MIN]]
;
%a_ext = sext <2 x i32> %a to <2 x i64>
@@ -406,11 +419,12 @@ define i64 @umin_sext2(i32 %a) {
ret i64 %min
}
+; FIXME
define <2 x i64> @umin_sext2_vec(<2 x i32> %a) {
; CHECK-LABEL: @umin_sext2_vec(
; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> %a to <2 x i64>
-; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i64> [[A_EXT]], <i64 3, i64 3>
-; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> [[A_EXT]], <2 x i64> <i64 3, i64 3>
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> %a, <i32 2, i32 2>
+; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> <i64 3, i64 3>, <2 x i64> [[A_EXT]]
; CHECK-NEXT: ret <2 x i64> [[MIN]]
;
%a_ext = sext <2 x i32> %a to <2 x i64>
@@ -432,11 +446,12 @@ define i64 @umax_zext(i32 %a) {
ret i64 %max
}
+; FIXME
define <2 x i64> @umax_zext_vec(<2 x i32> %a) {
; CHECK-LABEL: @umax_zext_vec(
; CHECK-NEXT: [[A_EXT:%.*]] = zext <2 x i32> %a to <2 x i64>
-; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i64> [[A_EXT]], <i64 3, i64 3>
-; CHECK-NEXT: [[MAX:%.*]] = select <2 x i1> [[CMP]], <2 x i64> <i64 3, i64 3>, <2 x i64> [[A_EXT]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> %a, <i32 2, i32 2>
+; CHECK-NEXT: [[MAX:%.*]] = select <2 x i1> [[CMP]], <2 x i64> [[A_EXT]], <2 x i64> <i64 3, i64 3>
; CHECK-NEXT: ret <2 x i64> [[MAX]]
;
%a_ext = zext <2 x i32> %a to <2 x i64>
@@ -458,11 +473,12 @@ define i64 @umin_zext(i32 %a) {
ret i64 %min
}
+; FIXME
define <2 x i64> @umin_zext_vec(<2 x i32> %a) {
; CHECK-LABEL: @umin_zext_vec(
; CHECK-NEXT: [[A_EXT:%.*]] = zext <2 x i32> %a to <2 x i64>
-; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i64> [[A_EXT]], <i64 2, i64 2>
-; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> <i64 2, i64 2>, <2 x i64> [[A_EXT]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> %a, <i32 3, i32 3>
+; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> [[A_EXT]], <2 x i64> <i64 2, i64 2>
; CHECK-NEXT: ret <2 x i64> [[MIN]]
;
%a_ext = zext <2 x i32> %a to <2 x i64>
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