[llvm] r285835 - AMDGPU: Allow additional implicit operands on MOVRELS instructions

[Nicolai Haehnle via llvm-commits]

Author: nha
Date: Wed Nov  2 12:03:11 2016
New Revision: 285835

URL: http://llvm.org/viewvc/llvm-project?rev=285835&view=rev
Log:
AMDGPU: Allow additional implicit operands on MOVRELS instructions

Summary:
The post-RA scheduler occasionally uses additional implicit operands when
the vector implicit operand as a whole is killed, but some subregisters
are still live because they are directly referenced later. Unfortunately,
this seems incredibly subtle to reproduce.

Fixes piglit spec/glsl-110/execution/variable-indexing/vs-temp-array-mat2-index-wr.shader_test
and others.

Reviewers: arsenm, tstellarAMD

Subscribers: kzhuravl, wdng, yaxunl, tony-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D25656

Added:
    llvm/trunk/test/CodeGen/MIR/AMDGPU/movrels-bug.mir
Modified:
    llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=285835&r1=285834&r2=285835&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp Wed Nov  2 12:03:11 2016
@@ -2101,7 +2101,10 @@ bool SIInstrInfo::verifyInstruction(cons
       Desc.getNumImplicitUses();
     const unsigned NumImplicitOps = IsDst ? 2 : 1;
 
-    if (MI.getNumOperands() != StaticNumOps + NumImplicitOps) {
+    // Allow additional implicit operands. This allows a fixup done by the post
+    // RA scheduler where the main implicit operand is killed and implicit-defs
+    // are added for sub-registers that remain live after this instruction.
+    if (MI.getNumOperands() < StaticNumOps + NumImplicitOps) {
       ErrInfo = "missing implicit register operands";
       return false;
     }

Added: llvm/trunk/test/CodeGen/MIR/AMDGPU/movrels-bug.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/movrels-bug.mir?rev=285835&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/movrels-bug.mir (added)
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/movrels-bug.mir Wed Nov  2 12:03:11 2016
@@ -0,0 +1,31 @@
+# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass post-RA-sched  %s -o - | FileCheck %s
+
+# This tests a situation where a sub-register of a killed super-register operand
+# of V_MOVRELS happens to have an undef use later on. This leads to the post RA
+# scheduler adding additional implicit operands to the V_MOVRELS, which used
+# to fail machine instruction verification.
+
+--- |
+
+  define amdgpu_vs void @main(i32 %arg) { ret void }
+
+...
+---
+# CHECK-LABEL: name: main
+# CHECK-LABEL: bb.0:
+# CHECK: V_MOVRELS_B32_e32
+# CHECK: V_MAC_F32_e32
+
+name:            main
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    %m0 = S_MOV_B32 undef %sgpr0
+    V_MOVRELD_B32_e32 undef %vgpr2, 0, implicit %m0, implicit %exec, implicit-def %vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8, implicit undef %vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8(tied-def 4)
+    %m0 = S_MOV_B32 undef %sgpr0
+    %vgpr1 = V_MOVRELS_B32_e32 undef %vgpr1, implicit %m0, implicit %exec, implicit killed %vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8
+    %vgpr4 = V_MAC_F32_e32 undef %vgpr0, undef %vgpr0, undef %vgpr4, implicit %exec
+    EXP 15, 12, 0, 1, 0, undef %vgpr0, killed %vgpr1, killed %vgpr4, undef %vgpr0, implicit %exec
+    S_ENDPGM
+
+...