[llvm] r285794 - [llvm] FIx if-clause -Wmisleading-indentation issue.

[Kirill Bobyrev via llvm-commits]

Author: omtcyfz
Date: Wed Nov  2 05:00:40 2016
New Revision: 285794

URL: http://llvm.org/viewvc/llvm-project?rev=285794&view=rev
Log:
[llvm] FIx if-clause -Wmisleading-indentation issue.

While bootstrapping Clang with recent `gcc 6.2.0` I found a bug related to misleading indentation.

I believe, a pair of `{}` was forgotten, especially given the above similar piece of code:

```
      if (!RDef || !HII->isPredicable(*RDef)) {
        Done = coalesceRegisters(RD, RegisterRef(S1));
        if (Done) {
          UpdRegs.insert(RD.Reg);
          UpdRegs.insert(S1.getReg());
        }
      }
```

Reviewers: kparzysz

Differential Revision: https://reviews.llvm.org/D26204

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp?rev=285794&r1=285793&r2=285794&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp Wed Nov  2 05:00:40 2016
@@ -1174,12 +1174,13 @@ bool HexagonExpandCondsets::coalesceSegm
     if (!Done && S2.isReg()) {
       RegisterRef RS = S2;
       MachineInstr *RDef = getReachingDefForPred(RS, CI, RP.Reg, false);
-      if (!RDef || !HII->isPredicable(*RDef))
+      if (!RDef || !HII->isPredicable(*RDef)) {
         Done = coalesceRegisters(RD, RegisterRef(S2));
         if (Done) {
           UpdRegs.insert(RD.Reg);
           UpdRegs.insert(S2.getReg());
         }
+      }
     }
     Changed |= Done;
   }