[PATCH] D25500: AMDGPU: Workaround for instruction size with literals

Matt Arsenault via llvm-commits llvm-commits at lists.llvm.org
Tue Nov 1 12:24:12 PDT 2016


arsenm updated this revision to Diff 76614.
arsenm added a comment.

Fix crashes on new instructions. Some of the GPR indexing instructions are special cases because they have special immediates in place of the normal behaving src0/src1. Add a bit to know that checking the operands should be skipped


https://reviews.llvm.org/D25500

Files:
  lib/Target/AMDGPU/SIDefines.h
  lib/Target/AMDGPU/SIInstrFormats.td
  lib/Target/AMDGPU/SIInstrInfo.cpp
  lib/Target/AMDGPU/SIInstrInfo.h
  lib/Target/AMDGPU/SOPInstructions.td

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D25500.76614.patch
Type: text/x-patch
Size: 3204 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20161101/a3280c70/attachment.bin>


More information about the llvm-commits mailing list