[llvm] r285622 - Fix per-processor model scheduler definition completeness check

[Ulrich Weigand via llvm-commits]

Author: uweigand
Date: Mon Oct 31 13:59:52 2016
New Revision: 285622

URL: http://llvm.org/viewvc/llvm-project?rev=285622&view=rev
Log:
Fix per-processor model scheduler definition completeness check

The CodeGenSchedModels::checkCompleteness routine in TableGen/
CodeGenSchedule.cpp is supposed to verify for each processor
model that is marked as "complete" that it actually defines a
scheduling class for each instruction.

However, this did not work correctly due to an incorrect
check whether a scheduling class has an itinerary.

Reviewer: atrick
Differential revision: https://reviews.llvm.org/D26156


Modified:
    llvm/trunk/utils/TableGen/CodeGenSchedule.cpp

Modified: llvm/trunk/utils/TableGen/CodeGenSchedule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenSchedule.cpp?rev=285622&r1=285621&r2=285622&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenSchedule.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenSchedule.cpp Mon Oct 31 13:59:52 2016
@@ -1567,7 +1567,8 @@ void CodeGenSchedModels::checkCompletene
       const CodeGenSchedClass &SC = getSchedClass(SCIdx);
       if (!SC.Writes.empty())
         continue;
-      if (SC.ItinClassDef != nullptr)
+      if (SC.ItinClassDef != nullptr &&
+          SC.ItinClassDef->getName() != "NoItinerary")
         continue;
 
       const RecVec &InstRWs = SC.InstRWs;