[llvm] r285615 - GlobalISel: allow truncating pointer casts on AArch64.

[Tim Northover via llvm-commits]

Author: tnorthover
Date: Mon Oct 31 13:31:09 2016
New Revision: 285615

URL: http://llvm.org/viewvc/llvm-project?rev=285615&view=rev
Log:
GlobalISel: allow truncating pointer casts on AArch64.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
    llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir

Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=285615&r1=285614&r2=285615&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Mon Oct 31 13:31:09 2016
@@ -748,6 +748,7 @@ bool AArch64InstructionSelector::select(
     return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
   }
 
+  case TargetOpcode::G_PTRTOINT:
   case TargetOpcode::G_TRUNC: {
     const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
     const LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
@@ -918,7 +919,6 @@ bool AArch64InstructionSelector::select(
 
 
   case TargetOpcode::G_INTTOPTR:
-  case TargetOpcode::G_PTRTOINT:
   case TargetOpcode::G_BITCAST:
     return selectCopy(I, TII, MRI, TRI, RBI);
 

Modified: llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp?rev=285615&r1=285614&r2=285615&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64LegalizerInfo.cpp Mon Oct 31 13:31:09 2016
@@ -169,7 +169,9 @@ AArch64LegalizerInfo::AArch64LegalizerIn
   setAction({G_FRAME_INDEX, p0}, Legal);
   setAction({G_GLOBAL_VALUE, p0}, Legal);
 
-  setAction({G_PTRTOINT, 0, s64}, Legal);
+  for (auto Ty : {s1, s8, s16, s32, s64})
+    setAction({G_PTRTOINT, 0, Ty}, Legal);
+
   setAction({G_PTRTOINT, 1, p0}, Legal);
 
   setAction({G_INTTOPTR, 0, p0}, Legal);

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir?rev=285615&r1=285614&r2=285615&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir Mon Oct 31 13:31:09 2016
@@ -2522,25 +2522,42 @@ regBankSelected: true
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr64all }
 # CHECK-NEXT:  - { id: 1, class: fpr64 }
-# CHECK-NEXT:  - { id: 2, class: gpr64all }
-# CHECK-NEXT:  - { id: 3, class: gpr64all }
+# CHECK-NEXT:  - { id: 2, class: gpr64 }
+# CHECK-NEXT:  - { id: 3, class: gpr64 }
+# CHECK-NEXT:  - { id: 4, class: gpr32 }
+# CHECK-NEXT:  - { id: 5, class: gpr32 }
+# CHECK-NEXT:  - { id: 6, class: gpr32 }
+# CHECK-NEXT:  - { id: 7, class: gpr32 }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: fpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+  - { id: 7, class: gpr }
 # CHECK:  body:
 # CHECK:    %0 = COPY %x0
 # CHECK:    %1 = COPY %0
 # CHECK:    %2 = COPY %0
 # CHECK:    %3 = COPY %2
+# CHECK:    %4 = COPY %2.sub_32
+# CHECK:    %5 = COPY %2.sub_32
+# CHECK:    %6 = COPY %2.sub_32
+# CHECK:    %7 = COPY %2.sub_32
 body:             |
   bb.0:
     liveins: %x0
     %0(s64) = COPY %x0
     %1(<8 x s8>) = G_BITCAST %0(s64)
     %2(p0) = G_INTTOPTR %0
+
     %3(s64) = G_PTRTOINT %2
+    %4(s32) = G_PTRTOINT %2
+    %5(s16) = G_PTRTOINT %2
+    %6(s8) = G_PTRTOINT %2
+    %7(s1) = G_PTRTOINT %2
 ...
 
 ---