[llvm] r285488 - AArch64DeadRegisterDefinitionsPass: Cleanup; NFC
Matthias Braun via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 28 18:03:41 PDT 2016
Author: matze
Date: Fri Oct 28 20:03:41 2016
New Revision: 285488
URL: http://llvm.org/viewvc/llvm-project?rev=285488&view=rev
Log:
AArch64DeadRegisterDefinitionsPass: Cleanup; NFC
- Fix doxygen file comment
- reduce indentation in loop
- Factor out some common subexpressions
- Move independent helper function out of class
- Fix Changed flag (this is not strictly NFC but a bugfix, but the flag
seems ignored anyway)
Modified:
llvm/trunk/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
Modified: llvm/trunk/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp?rev=285488&r1=285487&r2=285488&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp Fri Oct 28 20:03:41 2016
@@ -6,9 +6,9 @@
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
-// When allowed by the instruction, replace a dead definition of a GPR with
-// the zero register. This makes the code a bit friendlier towards the
-// hardware's register renamer.
+/// \file When allowed by the instruction, replace a dead definition of a GPR
+/// with the zero register. This makes the code a bit friendlier towards the
+/// hardware's register renamer.
//===----------------------------------------------------------------------===//
#include "AArch64.h"
@@ -32,12 +32,12 @@ namespace {
class AArch64DeadRegisterDefinitions : public MachineFunctionPass {
private:
const TargetRegisterInfo *TRI;
+ bool Changed;
bool implicitlyDefinesOverlappingReg(unsigned Reg, const MachineInstr &MI);
- bool processMachineBasicBlock(MachineBasicBlock &MBB);
- bool usesFrameIndex(const MachineInstr &MI);
+ void processMachineBasicBlock(MachineBasicBlock &MBB);
public:
static char ID; // Pass identification, replacement for typeid.
- explicit AArch64DeadRegisterDefinitions() : MachineFunctionPass(ID) {
+ AArch64DeadRegisterDefinitions() : MachineFunctionPass(ID) {
initializeAArch64DeadRegisterDefinitionsPass(
*PassRegistry::getPassRegistry());
}
@@ -71,16 +71,15 @@ bool AArch64DeadRegisterDefinitions::imp
return false;
}
-bool AArch64DeadRegisterDefinitions::usesFrameIndex(const MachineInstr &MI) {
- for (const MachineOperand &Op : MI.uses())
- if (Op.isFI())
+static bool usesFrameIndex(const MachineInstr &MI) {
+ for (const MachineOperand &MO : MI.uses())
+ if (MO.isFI())
return true;
return false;
}
-bool AArch64DeadRegisterDefinitions::processMachineBasicBlock(
+void AArch64DeadRegisterDefinitions::processMachineBasicBlock(
MachineBasicBlock &MBB) {
- bool Changed = false;
for (MachineInstr &MI : MBB) {
if (usesFrameIndex(MI)) {
// We need to skip this instruction because while it appears to have a
@@ -95,62 +94,62 @@ bool AArch64DeadRegisterDefinitions::pro
DEBUG(dbgs() << " Ignoring, XZR or WZR already used by the instruction\n");
continue;
}
- for (int i = 0, e = MI.getDesc().getNumDefs(); i != e; ++i) {
- MachineOperand &MO = MI.getOperand(i);
- if (MO.isReg() && MO.isDead() && MO.isDef()) {
- assert(!MO.isImplicit() && "Unexpected implicit def!");
- DEBUG(dbgs() << " Dead def operand #" << i << " in:\n ";
- MI.print(dbgs()));
- // Be careful not to change the register if it's a tied operand.
- if (MI.isRegTiedToUseOperand(i)) {
- DEBUG(dbgs() << " Ignoring, def is tied operand.\n");
- continue;
- }
- // Don't change the register if there's an implicit def of a subreg or
- // superreg.
- if (implicitlyDefinesOverlappingReg(MO.getReg(), MI)) {
- DEBUG(dbgs() << " Ignoring, implicitly defines overlap reg.\n");
- continue;
- }
- // Make sure the instruction take a register class that contains
- // the zero register and replace it if so.
- unsigned NewReg;
- switch (MI.getDesc().OpInfo[i].RegClass) {
- default:
- DEBUG(dbgs() << " Ignoring, register is not a GPR.\n");
- continue;
- case AArch64::GPR32RegClassID:
- NewReg = AArch64::WZR;
- break;
- case AArch64::GPR64RegClassID:
- NewReg = AArch64::XZR;
- break;
- }
- DEBUG(dbgs() << " Replacing with zero register. New:\n ");
- MO.setReg(NewReg);
- DEBUG(MI.print(dbgs()));
- ++NumDeadDefsReplaced;
- // Only replace one dead register, see check for zero register above.
+ const MCInstrDesc &Desc = MI.getDesc();
+ for (int I = 0, E = Desc.getNumDefs(); I != E; ++I) {
+ MachineOperand &MO = MI.getOperand(I);
+ if (!MO.isReg() || !MO.isDead() || !MO.isDef())
+ continue;
+ assert(!MO.isImplicit() && "Unexpected implicit def!");
+ DEBUG(dbgs() << " Dead def operand #" << I << " in:\n ";
+ MI.print(dbgs()));
+ // Be careful not to change the register if it's a tied operand.
+ if (MI.isRegTiedToUseOperand(I)) {
+ DEBUG(dbgs() << " Ignoring, def is tied operand.\n");
+ continue;
+ }
+ // Don't change the register if there's an implicit def of a subreg or
+ // superreg.
+ if (implicitlyDefinesOverlappingReg(MO.getReg(), MI)) {
+ DEBUG(dbgs() << " Ignoring, implicitly defines overlap reg.\n");
+ continue;
+ }
+ // Make sure the instruction take a register class that contains
+ // the zero register and replace it if so.
+ unsigned NewReg;
+ switch (Desc.OpInfo[I].RegClass) {
+ default:
+ DEBUG(dbgs() << " Ignoring, register is not a GPR.\n");
+ continue;
+ case AArch64::GPR32RegClassID:
+ NewReg = AArch64::WZR;
+ break;
+ case AArch64::GPR64RegClassID:
+ NewReg = AArch64::XZR;
break;
}
+ DEBUG(dbgs() << " Replacing with zero register. New:\n ");
+ MO.setReg(NewReg);
+ DEBUG(MI.print(dbgs()));
+ ++NumDeadDefsReplaced;
+ Changed = true;
+ // Only replace one dead register, see check for zero register above.
+ break;
}
}
- return Changed;
}
// Scan the function for instructions that have a dead definition of a
// register. Replace that register with the zero register when possible.
bool AArch64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
- TRI = MF.getSubtarget().getRegisterInfo();
- bool Changed = false;
- DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n");
-
if (skipFunction(*MF.getFunction()))
return false;
+ TRI = MF.getSubtarget().getRegisterInfo();
+ bool Changed = false;
+ DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n");
+ Changed = false;
for (auto &MBB : MF)
- if (processMachineBasicBlock(MBB))
- Changed = true;
+ processMachineBasicBlock(MBB);
return Changed;
}
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