[PATCH] D26098: [SelectionDAG] Fix a crash visiting `AND` nodes

[Davide Italiano via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL285480: [DAGCombiner] Fix a crash visiting `AND` nodes. (authored by davide).

Changed prior to commit:
  https://reviews.llvm.org/D26098?vs=76248&id=76276#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D26098

Files:
  llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/trunk/test/CodeGen/X86/pr30813.s


Index: llvm/trunk/test/CodeGen/X86/pr30813.s
===================================================================
--- llvm/trunk/test/CodeGen/X86/pr30813.s
+++ llvm/trunk/test/CodeGen/X86/pr30813.s
@@ -0,0 +1,20 @@
+	.text
+	.file	"/home/davide/work/llvm/test/CodeGen/X86/visitand-shift.ll"
+	.globl	patatino
+	.p2align	4, 0x90
+	.type	patatino, at function
+patatino:                               # @patatino
+	.cfi_startproc
+# BB#0:
+                                        # implicit-def: %RAX
+	movzwl	(%rax), %ecx
+	movl	%ecx, %eax
+                                        # implicit-def: %RDX
+	movq	%rax, (%rdx)
+	retq
+.Lfunc_end0:
+	.size	patatino, .Lfunc_end0-patatino
+	.cfi_endproc
+
+
+	.section	".note.GNU-stack","", at progbits
Index: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3046,6 +3046,11 @@
         unsigned Size = VT.getSizeInBits();
         const APInt &AndMask = CAnd->getAPIntValue();
         unsigned ShiftBits = CShift->getZExtValue();
+
+        // Bail out, this node will probably disappear anyway.
+        if (ShiftBits == 0)
+          return SDValue();
+
         unsigned MaskBits = AndMask.countTrailingOnes();
         EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), Size / 2);
 
@@ -3064,7 +3069,7 @@
           // extended to handle extensions mixed in.
 
           SDValue SL(N0);
-          assert(ShiftBits != 0 && MaskBits <= Size);
+          assert(MaskBits <= Size);
 
           // Extracting the highest bit of the low half.
           EVT ShiftVT = TLI.getShiftAmountTy(HalfVT, DAG.getDataLayout());


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