[PATCH] D26098: [SelectionDAG] Fix a crash visiting `AND` nodes
Davide Italiano via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 28 14:46:30 PDT 2016
davide updated this revision to Diff 76248.
davide added a comment.
Update correct revision.
https://reviews.llvm.org/D26098
Files:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
test/CodeGen/X86/pr30813.ll
Index: test/CodeGen/X86/pr30813.ll
===================================================================
--- /dev/null
+++ test/CodeGen/X86/pr30813.ll
@@ -0,0 +1,27 @@
+; RUN: llc -O0 %s -o - | FileCheck %s
+; CHECK: patatino:
+; CHECK: .cfi_startproc
+; CHECK: movzwl (%rax), %ecx
+; CHECK: movl %ecx, %eax
+; CHECK: movq %rax, (%rdx)
+; CHECK: retq
+
+define void @patatino() {
+ %tmp = load i16, i16* undef, align 8
+ %conv18098 = sext i16 %tmp to i64
+ %and1 = and i64 %conv18098, -1
+ %cmp = icmp ult i64 -1, undef
+ %conv = sext i1 %cmp to i64
+ %load1 = load i48, i48* undef, align 8
+ %bf.cast18158 = sext i48 %load1 to i64
+ %conv18159 = trunc i64 %bf.cast18158 to i32
+ %conv18160 = sext i32 %conv18159 to i64
+ %div18162 = udiv i64 %conv, %conv18160
+ %and18163 = and i64 %conv18098, %div18162
+ %shr18164 = lshr i64 %and1, %and18163
+ %conv18165 = trunc i64 %shr18164 to i16
+ %conv18166 = zext i16 %conv18165 to i64
+ store i64 %conv18166, i64* undef, align 8
+ store i48 undef, i48* undef, align 8
+ ret void
+}
Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3049,6 +3049,10 @@
unsigned MaskBits = AndMask.countTrailingOnes();
EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), Size / 2);
+ // Bail out, this node will probably disappear anyway.
+ if (ShiftBits == 0)
+ return SDValue();
+
if (APIntOps::isMask(AndMask) &&
// Required bits must not span the two halves of the integer and
// must fit in the half size type.
@@ -3064,7 +3068,7 @@
// extended to handle extensions mixed in.
SDValue SL(N0);
- assert(ShiftBits != 0 && MaskBits <= Size);
+ assert(MaskBits <= Size);
// Extracting the highest bit of the low half.
EVT ShiftVT = TLI.getShiftAmountTy(HalfVT, DAG.getDataLayout());
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