[PATCH] D26095: Implement vector shift builtins - llvm portion.
Tony Jiang via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 28 14:36:22 PDT 2016
jtony updated this revision to Diff 76246.
jtony added a comment.
Fix the spacing and alignment problem in the previous patch.
https://reviews.llvm.org/D26095
Files:
include/llvm/IR/IntrinsicsPowerPC.td
lib/Target/PowerPC/PPCInstrAltivec.td
test/CodeGen/PowerPC/vsx-p9.ll
Index: test/CodeGen/PowerPC/vsx-p9.ll
===================================================================
--- test/CodeGen/PowerPC/vsx-p9.ll
+++ test/CodeGen/PowerPC/vsx-p9.ll
@@ -167,4 +167,27 @@
; Function Attrs: nounwind readnone
declare <2 x double> @llvm.ppc.vsx.xviexpdp(<2 x i64>, <2 x i64>)
+define <16 x i8> @testVSLV(<16 x i8> %a, <16 x i8> %b) {
+entry:
+ %0 = tail call <16 x i8> @llvm.ppc.altivec.vslv(<16 x i8> %a, <16 x i8> %b)
+ ret <16 x i8> %0
+; CHECK-LABEL: testVSLV
+; CHECK: vslv 2, 2, 3
+; CHECK: blr
+}
+; Function Attrs: nounwind readnone
+declare <16 x i8> @llvm.ppc.altivec.vslv(<16 x i8>, <16 x i8>)
+
+; Function Attrs: nounwind readnone
+define <16 x i8> @testVSRV(<16 x i8> %a, <16 x i8> %b) {
+entry:
+ %0 = tail call <16 x i8> @llvm.ppc.altivec.vsrv(<16 x i8> %a, <16 x i8> %b)
+ ret <16 x i8> %0
+; CHECK-LABEL: testVSRV
+; CHECK: vsrv 2, 2, 3
+; CHECK: blr
+}
+; Function Attrs: nounwind readnone
+declare <16 x i8> @llvm.ppc.altivec.vsrv(<16 x i8>, <16 x i8>)
+
declare void @sink(...)
Index: lib/Target/PowerPC/PPCInstrAltivec.td
===================================================================
--- lib/Target/PowerPC/PPCInstrAltivec.td
+++ lib/Target/PowerPC/PPCInstrAltivec.td
@@ -1335,8 +1335,10 @@
def VRLDMI : VX1_VT5_VA5_VB5<197, "vrldmi", []>;
// Vector Shift Left/Right
-def VSLV : VX1_VT5_VA5_VB5<1860, "vslv", []>;
-def VSRV : VX1_VT5_VA5_VB5<1796, "vsrv", []>;
+def VSLV : VX1_VT5_VA5_VB5<1860, "vslv",
+ [(set v16i8 : $vD, (int_ppc_altivec_vslv v16i8 : $vA, v16i8 : $vB))]>;
+def VSRV : VX1_VT5_VA5_VB5<1796, "vsrv",
+ [(set v16i8 : $vD, (int_ppc_altivec_vsrv v16i8 : $vA, v16i8 : $vB))]>;
// Vector Multiply-by-10 (& Write Carry) Unsigned Quadword
def VMUL10UQ : VXForm_BX<513, (outs vrrc:$vD), (ins vrrc:$vA),
Index: include/llvm/IR/IntrinsicsPowerPC.td
===================================================================
--- include/llvm/IR/IntrinsicsPowerPC.td
+++ include/llvm/IR/IntrinsicsPowerPC.td
@@ -611,6 +611,8 @@
def int_ppc_altivec_vslo : PowerPC_Vec_WWW_Intrinsic<"vslo">;
def int_ppc_altivec_vslb : PowerPC_Vec_BBB_Intrinsic<"vslb">;
+def int_ppc_altivec_vslv : PowerPC_Vec_BBB_Intrinsic<"vslv">;
+def int_ppc_altivec_vsrv : PowerPC_Vec_BBB_Intrinsic<"vsrv">;
def int_ppc_altivec_vslh : PowerPC_Vec_HHH_Intrinsic<"vslh">;
def int_ppc_altivec_vslw : PowerPC_Vec_WWW_Intrinsic<"vslw">;
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