[PATCH] D26098: [SelectionDAG] Fix a crash visiting `AND` nodes

[Davide Italiano via llvm-commits]

davide created this revision.
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When visiting we crash in  `t16: i64 = srl t40, Constant:i8<0>` because we don't expect a shift-by-zero in `visitAndLike`.
I don't see a reason why this is invalid, and as discussed with Matt on IRC (which originally introduced this assertion) is probably fine to relax the condition a bit.

  SelectionDAG has 11 nodes:
    t0: ch = EntryToken
    t2: i64 = Constant<0>
    t29: i32,ch = load<LD2[undef](align=8), sext from i16> t0, undef:i64, undef:i64
      t19: ch = TokenFactor t29:1, t0
          t40: i64 = sign_extend t29
        t16: i64 = srl t40, Constant:i8<0>
      t24: i64 = and t16, Constant:i64<65535>
    t20: ch = store<ST8[undef]> t19, t24, undef:i64, undef:i64


https://reviews.llvm.org/D26098

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/X86/visitand-shift.ll


Index: test/CodeGen/X86/visitand-shift.ll
===================================================================
--- /dev/null
+++ test/CodeGen/X86/visitand-shift.ll
@@ -0,0 +1,27 @@
+; RUN: llc -O0 %s -o - | FileCheck %s
+; CHECK: patatino:
+; CHECK:         .cfi_startproc
+; CHECK:         movzwl  (%rax), %ecx
+; CHECK:         movl    %ecx, %eax
+; CHECK:         movq    %rax, (%rdx)
+; CHECK:         retq
+
+define void @patatino() {
+  %tmp = load i16, i16* undef, align 8
+  %conv18098 = sext i16 %tmp to i64
+  %and1 = and i64 %conv18098, -1
+  %cmp = icmp ult i64 -1, undef
+  %conv = sext i1 %cmp to i64
+  %load1 = load i48, i48* undef, align 8
+  %bf.cast18158 = sext i48 %load1 to i64
+  %conv18159 = trunc i64 %bf.cast18158 to i32
+  %conv18160 = sext i32 %conv18159 to i64
+  %div18162 = udiv i64 %conv, %conv18160
+  %and18163 = and i64 %conv18098, %div18162
+  %shr18164 = lshr i64 %and1, %and18163
+  %conv18165 = trunc i64 %shr18164 to i16
+  %conv18166 = zext i16 %conv18165 to i64
+  store i64 %conv18166, i64* undef, align 8
+  store i48 undef, i48* undef, align 8
+  ret void
+}
Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3064,7 +3064,7 @@
           // extended to handle extensions mixed in.
 
           SDValue SL(N0);
-          assert(ShiftBits != 0 && MaskBits <= Size);
+          assert(MaskBits <= Size);
 
           // Extracting the highest bit of the low half.
           EVT ShiftVT = TLI.getShiftAmountTy(HalfVT, DAG.getDataLayout());


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