[PATCH] D18049: AMDGPU/SI: Make i16 a legal type for VI subtargets

[Matt Arsenault via llvm-commits]

arsenm added inline comments.


================
Comment at: lib/Target/AMDGPU/BUFInstructions.td:960
+
+let Predicates = [isVI] in {
+
----------------
This can be refined to a has 16-bit predicate


================
Comment at: lib/Target/AMDGPU/VOP1Instructions.td:614-618
+/*
+def : ZExt_i16_i1_Pat<zext>;
+def : ZExt_i16_i1_Pat<sext>;
+def : ZExt_i16_i1_Pat<anyext>;
+*/
----------------
Commented out code


================
Comment at: lib/Target/AMDGPU/VOP2Instructions.td:348
 
+let Predicates = [isVI] in {
+
----------------
This should only need to be around the actual defs, not the multiclasses 


================
Comment at: lib/Target/AMDGPU/VOP2Instructions.td:355
+  (op i16:$src0, i16:$src1),
+  (inst i16:$src0, i16:$src1)
+>;
----------------
I don't think you need to repeat the type in the output here


================
Comment at: lib/Target/AMDGPU/VOP3Instructions.td:232
+
+multiclass Tenary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2, Instruction inst, SDPatternOperator op3> {
+def : Pat<
----------------
Line wrapping


https://reviews.llvm.org/D18049