[llvm] r285338 - AMDGPU/SI: Handle s_setreg hazard in GCNHazardRecognizer
Tom Stellard via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 27 13:39:09 PDT 2016
Author: tstellar
Date: Thu Oct 27 15:39:09 2016
New Revision: 285338
URL: http://llvm.org/viewvc/llvm-project?rev=285338&view=rev
Log:
AMDGPU/SI: Handle s_setreg hazard in GCNHazardRecognizer
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye
Differential Revision: https://reviews.llvm.org/D25528
Modified:
llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.h
llvm/trunk/test/CodeGen/MIR/AMDGPU/inserted-wait-states.mir
Modified: llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.cpp?rev=285338&r1=285337&r2=285338&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.cpp Thu Oct 27 15:39:09 2016
@@ -76,6 +76,9 @@ GCNHazardRecognizer::getHazardType(SUnit
if (isSGetReg(MI->getOpcode()) && checkGetRegHazards(MI) > 0)
return NoopHazard;
+ if (isSSetReg(MI->getOpcode()) && checkSetRegHazards(MI) > 0)
+ return NoopHazard;
+
return NoHazard;
}
@@ -99,6 +102,9 @@ unsigned GCNHazardRecognizer::PreEmitNoo
if (isSGetReg(MI->getOpcode()))
return std::max(0, checkGetRegHazards(MI));
+ if (isSSetReg(MI->getOpcode()))
+ return std::max(0, checkSetRegHazards(MI));
+
return 0;
}
@@ -331,3 +337,16 @@ int GCNHazardRecognizer::checkGetRegHaza
return GetRegWaitStates - WaitStatesNeeded;
}
+
+int GCNHazardRecognizer::checkSetRegHazards(MachineInstr *SetRegInstr) {
+ const SIInstrInfo *TII = ST.getInstrInfo();
+ unsigned HWReg = getHWReg(TII, *SetRegInstr);
+
+ const int SetRegWaitStates =
+ ST.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ? 1 : 2;
+ auto IsHazardFn = [TII, HWReg] (MachineInstr *MI) {
+ return HWReg == getHWReg(TII, *MI);
+ };
+ int WaitStatesNeeded = getWaitStatesSinceSetReg(IsHazardFn);
+ return SetRegWaitStates - WaitStatesNeeded;
+}
Modified: llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.h?rev=285338&r1=285337&r2=285338&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/GCNHazardRecognizer.h Thu Oct 27 15:39:09 2016
@@ -46,6 +46,7 @@ class GCNHazardRecognizer final : public
int checkDPPHazards(MachineInstr *DPP);
int checkDivFMasHazards(MachineInstr *DivFMas);
int checkGetRegHazards(MachineInstr *GetRegInstr);
+ int checkSetRegHazards(MachineInstr *SetRegInstr);
public:
GCNHazardRecognizer(const MachineFunction &MF);
// We can only issue one instruction per cycle.
Modified: llvm/trunk/test/CodeGen/MIR/AMDGPU/inserted-wait-states.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/inserted-wait-states.mir?rev=285338&r1=285337&r2=285338&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/inserted-wait-states.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/inserted-wait-states.mir Thu Oct 27 15:39:09 2016
@@ -1,40 +1,43 @@
-# RUN: llc -march=amdgcn -run-pass post-RA-hazard-rec %s -o - | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN
+# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass post-RA-hazard-rec %s -o - | FileCheck %s -check-prefixes=GCN,VI
--- |
define void @div_fmas() { ret void }
define void @s_getreg() { ret void }
+ define void @s_setreg() { ret void }
...
---
-# CHECK-LABEL: name: div_fmas
+# GCN-LABEL: name: div_fmas
-# CHECK-LABEL: bb.0:
-# CHECK: S_MOV_B64
-# CHECK-NOT: S_NOP
-# CHECK: V_DIV_FMAS
-
-# CHECK-LABEL: bb.1:
-# CHECK: V_CMP_EQ_I32
-# CHECK: S_NOP
-# CHECK: S_NOP
-# CHECK: S_NOP
-# CHECK: S_NOP
-# CHECK: V_DIV_FMAS_F32
-
-# CHECK-LABEL: bb.2:
-# CHECK: V_CMP_EQ_I32
-# CHECK: S_NOP
-# CHECK: S_NOP
-# CHECK: S_NOP
-# CHECK: S_NOP
-# CHECK: V_DIV_FMAS_F32
-
-# CHECK-LABEL: bb.3:
-# CHECK: V_DIV_SCALE_F32
-# CHECK: S_NOP
-# CHECK: S_NOP
-# CHECK: S_NOP
-# CHECK: S_NOP
-# CHECK: V_DIV_FMAS_F32
+# GCN-LABEL: bb.0:
+# GCN: S_MOV_B64
+# GCN-NOT: S_NOP
+# GCN: V_DIV_FMAS
+
+# GCN-LABEL: bb.1:
+# GCN: V_CMP_EQ_I32
+# GCN: S_NOP
+# GCN: S_NOP
+# GCN: S_NOP
+# GCN: S_NOP
+# GCN: V_DIV_FMAS_F32
+
+# GCN-LABEL: bb.2:
+# GCN: V_CMP_EQ_I32
+# GCN: S_NOP
+# GCN: S_NOP
+# GCN: S_NOP
+# GCN: S_NOP
+# GCN: V_DIV_FMAS_F32
+
+# GCN-LABEL: bb.3:
+# GCN: V_DIV_SCALE_F32
+# GCN: S_NOP
+# GCN: S_NOP
+# GCN: S_NOP
+# GCN: S_NOP
+# GCN: V_DIV_FMAS_F32
name: div_fmas
body: |
@@ -65,28 +68,28 @@ body: |
...
---
-# CHECK-LABEL: name: s_getreg
+# GCN-LABEL: name: s_getreg
-# CHECK-LABEL: bb.0:
-# CHECK: S_SETREG
-# CHECK: S_NOP 0
-# CHECK: S_NOP 0
-# CHECK: S_GETREG
-
-# CHECK-LABEL: bb.1:
-# CHECK: S_SETREG_IMM32
-# CHECK: S_NOP 0
-# CHECK: S_NOP 0
-# CHECK: S_GETREG
-
-# CHECK-LABEL: bb.2:
-# CHECK: S_SETREG
-# CHECK: S_NOP 0
-# CHECK: S_GETREG
-
-# CHECK-LABEL: bb.3:
-# CHECK: S_SETREG
-# CHECK-NEXT: S_GETREG
+# GCN-LABEL: bb.0:
+# GCN: S_SETREG
+# GCN: S_NOP 0
+# GCN: S_NOP 0
+# GCN: S_GETREG
+
+# GCN-LABEL: bb.1:
+# GCN: S_SETREG_IMM32
+# GCN: S_NOP 0
+# GCN: S_NOP 0
+# GCN: S_GETREG
+
+# GCN-LABEL: bb.2:
+# GCN: S_SETREG
+# GCN: S_NOP 0
+# GCN: S_GETREG
+
+# GCN-LABEL: bb.3:
+# GCN: S_SETREG
+# GCN-NEXT: S_GETREG
name: s_getreg
@@ -115,3 +118,44 @@ body: |
%sgpr1 = S_GETREG_B32 1
S_ENDPGM
...
+
+...
+---
+# GCN-LABEL: name: s_setreg
+
+# GCN-LABEL: bb.0:
+# GCN: S_SETREG
+# GCN: S_NOP 0
+# VI: S_NOP 0
+# GCN-NEXT: S_SETREG
+
+# GCN-LABEL: bb.1:
+# GCN: S_SETREG
+# GCN: S_NOP 0
+# VI: S_NOP 0
+# GCN-NEXT: S_SETREG
+
+# GCN-LABEL: bb.2:
+# GCN: S_SETREG
+# GCN-NEXT: S_SETREG
+
+name: s_setreg
+
+body: |
+ bb.0:
+ successors: %bb.1
+ S_SETREG_B32 %sgpr0, 1
+ S_SETREG_B32 %sgpr1, 1
+ S_BRANCH %bb.1
+
+ bb.1:
+ successors: %bb.2
+ S_SETREG_B32 %sgpr0, 64
+ S_SETREG_B32 %sgpr1, 128
+ S_BRANCH %bb.2
+
+ bb.2:
+ S_SETREG_B32 %sgpr0, 1
+ S_SETREG_B32 %sgpr1, 0
+ S_ENDPGM
+...
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