[PATCH] D25788: AMDGPU/SI: Don't emit multi-dword flat memory ops when they might access scratch

[Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL285198: AMDGPU/SI: Don't emit multi-dword flat memory ops when they might access scratch (authored by tstellar).

Changed prior to commit:
  https://reviews.llvm.org/D25788?vs=75206&id=75889#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D25788

Files:
  llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/trunk/test/CodeGen/AMDGPU/flat-address-space.ll


Index: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -2591,6 +2591,14 @@
     return DAG.getMergeValues(Ops, DL);
   }
 
+  MachineFunction &MF = DAG.getMachineFunction();
+  SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
+  // If there is a possibilty that flat instruction access scratch memory
+  // then we need to use the same legalization rules we use for private.
+  if (AS == AMDGPUAS::FLAT_ADDRESS)
+    AS = MFI->hasFlatScratchInit() ?
+         AMDGPUAS::PRIVATE_ADDRESS : AMDGPUAS::GLOBAL_ADDRESS;
+
   unsigned NumElements = MemVT.getVectorNumElements();
   switch (AS) {
   case AMDGPUAS::CONSTANT_ADDRESS:
@@ -2890,6 +2898,14 @@
     return expandUnalignedStore(Store, DAG);
   }
 
+  MachineFunction &MF = DAG.getMachineFunction();
+  SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
+  // If there is a possibilty that flat instruction access scratch memory
+  // then we need to use the same legalization rules we use for private.
+  if (AS == AMDGPUAS::FLAT_ADDRESS)
+    AS = MFI->hasFlatScratchInit() ?
+         AMDGPUAS::PRIVATE_ADDRESS : AMDGPUAS::GLOBAL_ADDRESS;
+
   unsigned NumElements = VT.getVectorNumElements();
   switch (AS) {
   case AMDGPUAS::GLOBAL_ADDRESS:
Index: llvm/trunk/test/CodeGen/AMDGPU/flat-address-space.ll
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/flat-address-space.ll
+++ llvm/trunk/test/CodeGen/AMDGPU/flat-address-space.ll
@@ -1,5 +1,6 @@
-; RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=bonaire < %s | FileCheck %s
-; RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga < %s | FileCheck %s
+; RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=bonaire < %s | FileCheck  %s
+; RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga < %s | FileCheck  %s
+; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=CHECK,HSA %s
 
 ; Disable optimizations in case there are optimizations added that
 ; specialize away generic pointer accesses.
@@ -149,6 +150,28 @@
   ret void
 }
 
+; CHECK-LABEL: flat_scratch_multidword_load:
+; HSA: flat_load_dword
+; HSA: flat_load_dword
+; FIXME: These tests are broken for os = mesa3d, becasue it doesn't initialize flat_scr
+define void @flat_scratch_multidword_load() {
+  %scratch = alloca <2 x i32>
+  %fptr = addrspacecast <2 x i32>* %scratch to <2 x i32> addrspace(4)*
+  %ld = load volatile <2 x i32>, <2 x i32> addrspace(4)* %fptr
+  ret void
+}
+
+; CHECK-LABEL: flat_scratch_multidword_store:
+; HSA: flat_store_dword
+; HSA: flat_store_dword
+; FIXME: These tests are broken for os = mesa3d, becasue it doesn't initialize flat_scr
+define void @flat_scratch_multidword_store() {
+  %scratch = alloca <2 x i32>
+  %fptr = addrspacecast <2 x i32>* %scratch to <2 x i32> addrspace(4)*
+  store volatile <2 x i32> zeroinitializer, <2 x i32> addrspace(4)* %fptr
+  ret void
+}
+
 attributes #0 = { nounwind }
 attributes #1 = { nounwind convergent }
 attributes #3 = { nounwind readnone }


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