[llvm] r285195 - [InstCombine] consolidate zext tests and auto-generate checks; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 26 07:08:49 PDT 2016
Author: spatel
Date: Wed Oct 26 09:08:49 2016
New Revision: 285195
URL: http://llvm.org/viewvc/llvm-project?rev=285195&view=rev
Log:
[InstCombine] consolidate zext tests and auto-generate checks; NFC
Removed:
llvm/trunk/test/Transforms/InstCombine/apint-zext1.ll
llvm/trunk/test/Transforms/InstCombine/apint-zext2.ll
Modified:
llvm/trunk/test/Transforms/InstCombine/zext.ll
Removed: llvm/trunk/test/Transforms/InstCombine/apint-zext1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/apint-zext1.ll?rev=285194&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/apint-zext1.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/apint-zext1.ll (removed)
@@ -1,11 +0,0 @@
-; Tests to make sure elimination of casts is working correctly
-; This test is for Integer BitWidth <= 64 && BitWidth % 2 != 0.
-; RUN: opt < %s -instcombine -S | FileCheck %s
-
-define i47 @test_sext_zext(i11 %A) {
- %c1 = zext i11 %A to i39
- %c2 = sext i39 %c1 to i47
- ret i47 %c2
-; CHECK: %c2 = zext i11 %A to i47
-; CHECK: ret i47 %c2
-}
Removed: llvm/trunk/test/Transforms/InstCombine/apint-zext2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/apint-zext2.ll?rev=285194&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/apint-zext2.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/apint-zext2.ll (removed)
@@ -1,11 +0,0 @@
-; Tests to make sure elimination of casts is working correctly
-; This test is for Integer BitWidth > 64 && BitWidth <= 1024.
-; RUN: opt < %s -instcombine -S | FileCheck %s
-
-define i1024 @test_sext_zext(i77 %A) {
- %c1 = zext i77 %A to i533
- %c2 = sext i533 %c1 to i1024
- ret i1024 %c2
-; CHECK: %c2 = zext i77 %A to i1024
-; CHECK: ret i1024 %c2
-}
Modified: llvm/trunk/test/Transforms/InstCombine/zext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/zext.ll?rev=285195&r1=285194&r2=285195&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/zext.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/zext.ll Wed Oct 26 09:08:49 2016
@@ -71,13 +71,15 @@ define <2 x i64> @fold_xor_zext_sandwich
}
; Assert that zexts in and(zext(icmp), zext(icmp)) can be folded.
-; CHECK-LABEL: @fold_and_zext_icmp(
-; CHECK-NEXT: [[ICMP1:%.*]] = icmp sgt i64 %a, %b
-; CHECK-NEXT: [[ICMP2:%.*]] = icmp slt i64 %a, %c
-; CHECK-NEXT: [[AND:%.*]] = and i1 [[ICMP1]], [[ICMP2]]
-; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[AND]] to i8
-; CHECK-NEXT: ret i8 [[ZEXT]]
+
define i8 @fold_and_zext_icmp(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: @fold_and_zext_icmp(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i64 %a, %b
+; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i64 %a, %c
+; CHECK-NEXT: [[TMP3:%.*]] = and i1 [[TMP1]], [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i1 [[TMP3]] to i8
+; CHECK-NEXT: ret i8 [[TMP4]]
+;
%1 = icmp sgt i64 %a, %b
%2 = zext i1 %1 to i8
%3 = icmp slt i64 %a, %c
@@ -87,13 +89,15 @@ define i8 @fold_and_zext_icmp(i64 %a, i6
}
; Assert that zexts in or(zext(icmp), zext(icmp)) can be folded.
-; CHECK-LABEL: @fold_or_zext_icmp(
-; CHECK-NEXT: [[ICMP1:%.*]] = icmp sgt i64 %a, %b
-; CHECK-NEXT: [[ICMP2:%.*]] = icmp slt i64 %a, %c
-; CHECK-NEXT: [[OR:%.*]] = or i1 [[ICMP1]], [[ICMP2]]
-; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[OR]] to i8
-; CHECK-NEXT: ret i8 [[ZEXT]]
+
define i8 @fold_or_zext_icmp(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: @fold_or_zext_icmp(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i64 %a, %b
+; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i64 %a, %c
+; CHECK-NEXT: [[TMP3:%.*]] = or i1 [[TMP1]], [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i1 [[TMP3]] to i8
+; CHECK-NEXT: ret i8 [[TMP4]]
+;
%1 = icmp sgt i64 %a, %b
%2 = zext i1 %1 to i8
%3 = icmp slt i64 %a, %c
@@ -103,13 +107,15 @@ define i8 @fold_or_zext_icmp(i64 %a, i64
}
; Assert that zexts in xor(zext(icmp), zext(icmp)) can be folded.
-; CHECK-LABEL: @fold_xor_zext_icmp(
-; CHECK-NEXT: [[ICMP1:%.*]] = icmp sgt i64 %a, %b
-; CHECK-NEXT: [[ICMP2:%.*]] = icmp slt i64 %a, %c
-; CHECK-NEXT: [[XOR:%.*]] = xor i1 [[ICMP1]], [[ICMP2]]
-; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[XOR]] to i8
-; CHECK-NEXT: ret i8 [[ZEXT]]
+
define i8 @fold_xor_zext_icmp(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: @fold_xor_zext_icmp(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i64 %a, %b
+; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i64 %a, %c
+; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP1]], [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = zext i1 [[TMP3]] to i8
+; CHECK-NEXT: ret i8 [[TMP4]]
+;
%1 = icmp sgt i64 %a, %b
%2 = zext i1 %1 to i8
%3 = icmp slt i64 %a, %c
@@ -120,15 +126,17 @@ define i8 @fold_xor_zext_icmp(i64 %a, i6
; Assert that zexts in logic(zext(icmp), zext(icmp)) are also folded accross
; nested logical operators.
-; CHECK-LABEL: @fold_nested_logic_zext_icmp(
-; CHECK-NEXT: [[ICMP1:%.*]] = icmp sgt i64 %a, %b
-; CHECK-NEXT: [[ICMP2:%.*]] = icmp slt i64 %a, %c
-; CHECK-NEXT: [[AND:%.*]] = and i1 [[ICMP1]], [[ICMP2]]
-; CHECK-NEXT: [[ICMP3:%.*]] = icmp eq i64 %a, %d
-; CHECK-NEXT: [[OR:%.*]] = or i1 [[AND]], [[ICMP3]]
-; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[OR]] to i8
-; CHECK-NEXT: ret i8 [[ZEXT]]
+
define i8 @fold_nested_logic_zext_icmp(i64 %a, i64 %b, i64 %c, i64 %d) {
+; CHECK-LABEL: @fold_nested_logic_zext_icmp(
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i64 %a, %b
+; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i64 %a, %c
+; CHECK-NEXT: [[TMP3:%.*]] = and i1 [[TMP1]], [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 %a, %d
+; CHECK-NEXT: [[TMP5:%.*]] = or i1 [[TMP3]], [[TMP4]]
+; CHECK-NEXT: [[TMP6:%.*]] = zext i1 [[TMP5]] to i8
+; CHECK-NEXT: ret i8 [[TMP6]]
+;
%1 = icmp sgt i64 %a, %b
%2 = zext i1 %1 to i8
%3 = icmp slt i64 %a, %c
@@ -139,3 +147,28 @@ define i8 @fold_nested_logic_zext_icmp(i
%8 = or i8 %5, %7
ret i8 %8
}
+
+; This test is for Integer BitWidth > 64 && BitWidth <= 1024.
+
+define i1024 @sext_zext_apint1(i77 %A) {
+; CHECK-LABEL: @sext_zext_apint1(
+; CHECK-NEXT: [[C2:%.*]] = zext i77 %A to i1024
+; CHECK-NEXT: ret i1024 [[C2]]
+;
+ %c1 = zext i77 %A to i533
+ %c2 = sext i533 %c1 to i1024
+ ret i1024 %c2
+}
+
+; This test is for Integer BitWidth <= 64 && BitWidth % 2 != 0.
+
+define i47 @sext_zext_apint2(i11 %A) {
+; CHECK-LABEL: @sext_zext_apint2(
+; CHECK-NEXT: [[C2:%.*]] = zext i11 %A to i47
+; CHECK-NEXT: ret i47 [[C2]]
+;
+ %c1 = zext i11 %A to i39
+ %c2 = sext i39 %c1 to i47
+ ret i47 %c2
+}
+
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