[llvm] r285118 - [DAGCombiner] Enable sdiv(x.y) -> udiv(x, y) combine for vectors

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Tue Oct 25 15:56:42 2016
New Revision: 285118

URL: http://llvm.org/viewvc/llvm-project?rev=285118&view=rev
Log:
[DAGCombiner] Enable sdiv(x.y) -> udiv(x,y) combine for vectors

SelectionDAG::SignBitIsZero (via SelectionDAG::computeKnownBits) has supported vectors since rL280927

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/X86/combine-sdiv.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=285118&r1=285117&r2=285118&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Oct 25 15:56:42 2016
@@ -2317,10 +2317,8 @@ SDValue DAGCombiner::visitSDIV(SDNode *N
 
   // If we know the sign bits of both operands are zero, strength reduce to a
   // udiv instead.  Handles (X&15) /s 4 -> X&15 >> 2
-  if (!VT.isVector()) {
-    if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
-      return DAG.getNode(ISD::UDIV, DL, N1.getValueType(), N0, N1);
-  }
+  if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
+    return DAG.getNode(ISD::UDIV, DL, N1.getValueType(), N0, N1);
 
   // fold (sdiv X, pow2) -> simple ops after legalize
   // FIXME: We check for the exact bit here because the generic lowering gives

Modified: llvm/trunk/test/CodeGen/X86/combine-sdiv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-sdiv.ll?rev=285118&r1=285117&r2=285118&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-sdiv.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-sdiv.ll Tue Oct 25 15:56:42 2016
@@ -82,52 +82,28 @@ define <4 x i32> @combine_vec_sdiv_by_po
 ; SSE:       # BB#0:
 ; SSE-NEXT:    pand {{.*}}(%rip), %xmm0
 ; SSE-NEXT:    pextrd $1, %xmm0, %eax
-; SSE-NEXT:    movl %eax, %ecx
-; SSE-NEXT:    sarl $31, %ecx
-; SSE-NEXT:    shrl $30, %ecx
-; SSE-NEXT:    addl %eax, %ecx
-; SSE-NEXT:    sarl $2, %ecx
-; SSE-NEXT:    pextrd $2, %xmm0, %eax
+; SSE-NEXT:    shrl $2, %eax
+; SSE-NEXT:    pextrd $2, %xmm0, %ecx
 ; SSE-NEXT:    pextrd $3, %xmm0, %edx
-; SSE-NEXT:    pinsrd $1, %ecx, %xmm0
-; SSE-NEXT:    movl %eax, %ecx
-; SSE-NEXT:    sarl $31, %ecx
-; SSE-NEXT:    shrl $29, %ecx
-; SSE-NEXT:    addl %eax, %ecx
-; SSE-NEXT:    sarl $3, %ecx
+; SSE-NEXT:    pinsrd $1, %eax, %xmm0
+; SSE-NEXT:    shrl $3, %ecx
 ; SSE-NEXT:    pinsrd $2, %ecx, %xmm0
-; SSE-NEXT:    movl %edx, %eax
-; SSE-NEXT:    sarl $31, %eax
-; SSE-NEXT:    shrl $28, %eax
-; SSE-NEXT:    addl %edx, %eax
-; SSE-NEXT:    sarl $4, %eax
-; SSE-NEXT:    pinsrd $3, %eax, %xmm0
+; SSE-NEXT:    shrl $4, %edx
+; SSE-NEXT:    pinsrd $3, %edx, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: combine_vec_sdiv_by_pos1:
 ; AVX:       # BB#0:
 ; AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
 ; AVX-NEXT:    vpextrd $1, %xmm0, %eax
-; AVX-NEXT:    movl %eax, %ecx
-; AVX-NEXT:    sarl $31, %ecx
-; AVX-NEXT:    shrl $30, %ecx
-; AVX-NEXT:    addl %eax, %ecx
-; AVX-NEXT:    sarl $2, %ecx
-; AVX-NEXT:    vpinsrd $1, %ecx, %xmm0, %xmm1
+; AVX-NEXT:    shrl $2, %eax
+; AVX-NEXT:    vpinsrd $1, %eax, %xmm0, %xmm1
 ; AVX-NEXT:    vpextrd $2, %xmm0, %eax
-; AVX-NEXT:    movl %eax, %ecx
-; AVX-NEXT:    sarl $31, %ecx
-; AVX-NEXT:    shrl $29, %ecx
-; AVX-NEXT:    addl %eax, %ecx
-; AVX-NEXT:    sarl $3, %ecx
-; AVX-NEXT:    vpinsrd $2, %ecx, %xmm1, %xmm1
+; AVX-NEXT:    shrl $3, %eax
+; AVX-NEXT:    vpinsrd $2, %eax, %xmm1, %xmm1
 ; AVX-NEXT:    vpextrd $3, %xmm0, %eax
-; AVX-NEXT:    movl %eax, %ecx
-; AVX-NEXT:    sarl $31, %ecx
-; AVX-NEXT:    shrl $28, %ecx
-; AVX-NEXT:    addl %eax, %ecx
-; AVX-NEXT:    sarl $4, %ecx
-; AVX-NEXT:    vpinsrd $3, %ecx, %xmm1, %xmm0
+; AVX-NEXT:    shrl $4, %eax
+; AVX-NEXT:    vpinsrd $3, %eax, %xmm1, %xmm0
 ; AVX-NEXT:    retq
   %1 = and <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>
   %2 = sdiv <4 x i32> %1, <i32 1, i32 4, i32 8, i32 16>