[PATCH] D25759: [AVX512][llvm] Adding missing instructions' variations

[coby via llvm-commits]

coby added a comment.

In https://reviews.llvm.org/D25759#575109, @craig.topper wrote:

> Also the Intel docs say zero masking for store instructions is a UD fault and not supported so I'm not sure the rest of this patch is correct.


Dear Craig, there's indeed a specific exclusion regarding store semantics (and possibly more) when destination is of memory type, one which i've obviously failed to observe.
Will see to the bottom of this, many thanks for pointing that out.


Repository:
  rL LLVM

https://reviews.llvm.org/D25759