[PATCH] D25795: [mips] synci microMIPS instruction definition.

[Simon Dardis via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL284962: [mips] synci microMIPS instruction definition. (authored by sdardis).

Changed prior to commit:
  https://reviews.llvm.org/D25795?vs=75224&id=75565#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D25795

Files:
  llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td
  llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
  llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
  llvm/trunk/test/MC/Mips/micromips/valid.s


Index: llvm/trunk/test/MC/Mips/micromips/valid.s
===================================================================
--- llvm/trunk/test/MC/Mips/micromips/valid.s
+++ llvm/trunk/test/MC/Mips/micromips/valid.s
@@ -207,3 +207,7 @@
 recip.d $f2, $f4            # CHECK: recip.d $f2, $f4       # encoding: [0x54,0x44,0x52,0x3b]
 rsqrt.s $f3, $f5            # CHECK: rsqrt.s $f3, $f5       # encoding: [0x54,0x65,0x02,0x3b]
 rsqrt.d $f2, $f4            # CHECK: rsqrt.d $f2, $f4       # encoding: [0x54,0x44,0x42,0x3b]
+sync                        # CHECK: sync                   # encoding: [0x00,0x00,0x6b,0x7c]
+sync 0                      # CHECK: sync 0                 # encoding: [0x00,0x00,0x6b,0x7c]
+sync 1                      # CHECK: sync 1                 # encoding: [0x00,0x01,0x6b,0x7c]
+synci 64($5)                # CHECK: synci 64($5)           # encoding: [0x42,0x00,0x00,0x40]
Index: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
===================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
@@ -927,6 +927,7 @@
 
   /// Control Instructions
   def SYNC_MM    : MMRel, SYNC_FT<"sync">, SYNC_FM_MM;
+  def SYNCI_MM   : MMRel, SYNCI_FT<"synci">, SYNCI_FM_MM;
   def BREAK_MM   : MMRel, BRK_FT<"break">, BRK_FM_MM;
   def SYSCALL_MM : MMRel, SYS_FT<"syscall", uimm10, II_SYSCALL>, SYS_FM_MM;
   def WAIT_MM    : WaitMM<"wait">, WAIT_FM_MM;
Index: llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td
===================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td
@@ -599,6 +599,17 @@
   let Inst{5-0}   = 0x3c;
 }
 
+class SYNCI_FM_MM : MMArch {
+  bits<5> rs;
+  bits<16> offset;
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b010000;
+  let Inst{25-21} = 0b10000;
+  let Inst{20-16} = rs;
+  let Inst{15-0}  = offset;
+}
+
 class BRK_FM_MM : MMArch {
   bits<10> code_1;
   bits<10> code_2;
Index: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
@@ -1874,10 +1874,10 @@
   def SDC3 : SW_FT3<"sdc3", COP3Opnd, II_SDC3, store>, LW_FM<0x3f>,
              ISA_MIPS2;
 }
-}
 
-def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS2;
-def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
+  def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS2;
+  def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
+}
 
 let AdditionalPredicates = [NotInMicroMips] in {
   def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm10, II_TEQ>, TEQ_FM<0x34>, ISA_MIPS2;


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