[PATCH] D25438: [mips] Fix Mips MSA instrinsics
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 21 08:46:18 PDT 2016
sdardis added a comment.
From immediates-bad.ll:
define void @addvi_d(<2 x i64> * %ptr) {
entry:
; CHECK-LABEL: addvi_d:
; CHECK: addv.d
%a = load <2 x i64>, <2 x i64> * %ptr, align 16
%r = call <2 x i64> @llvm.mips.addvi.d(<2 x i64> %a, i32 65)
store <2 x i64> %r, <2 x i64> * %ptr, align 16
ret void
}
will crash LLVM. Dump from llc:
Assertion failed: (width > BitWidth && "Invalid APInt ZeroExtend request"), function zext, file /Users/simon/dev/llvm/llvm2/llvm/lib/Support/APInt.cpp, line 981.
Stack dump:
0. Program arguments: /Users/simon/dev/llvm/llvm2/llvmgitsvnbuild/./bin/llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic
1. Running pass 'Function Pass Manager' on module '<stdin>'.
2. Running pass 'MIPS DAG->DAG Pattern Instruction Selection' on function '@addvi_d'
As you can seeI think there may be another solution though, which is to constrain the type of the immediate operand down to things like i5. I would have to reinvestigate.
Repository:
rL LLVM
https://reviews.llvm.org/D25438
More information about the llvm-commits
mailing list