[PATCH] D25818: [AArch64] Corrected spill size for DDD register class. NFCI

[Bjorn Pettersson via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL284814: [AArch64] Corrected spill size for DDD register class. NFCI (authored by bjope).

Changed prior to commit:
  https://reviews.llvm.org/D25818?vs=75282&id=75402#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D25818

Files:
  llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.td


Index: llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.td
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.td
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -422,7 +422,7 @@
   let Size = 128;
 }
 def DDD  : RegisterClass<"AArch64", [untyped], 64, (add DSeqTriples)> {
-  let Size = 196;
+  let Size = 192;
 }
 def DDDD : RegisterClass<"AArch64", [untyped], 64, (add DSeqQuads)> {
   let Size = 256;


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