[PATCH] D25862: X86: Improve BT instruction selection for 64-bit values.

[Peter Collingbourne via llvm-commits]

pcc created this revision.
pcc added a reviewer: spatel.
pcc added a subscriber: llvm-commits.

If a 64-bit value is tested against a bit which is known to be in the range
[0..31) (modulo 64), we can use the 32-bit BT instruction, which has a slightly
shorter encoding.


https://reviews.llvm.org/D25862

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/bt.ll


Index: llvm/test/CodeGen/X86/bt.ll
===================================================================
--- llvm/test/CodeGen/X86/bt.ll
+++ llvm/test/CodeGen/X86/bt.ll
@@ -596,3 +596,15 @@
   ret i1 %tobool
 }
 
+define zeroext i1 @extend(i32 %bit, i64 %bits) {
+; CHECK-LABEL: extend:
+; CHECK:       # BB#0:
+; CHECK-NEXT:  btl %edi, %esi
+entry:
+  %and = and i32 %bit, 31
+  %sh_prom = zext i32 %and to i64
+  %shl = shl i64 1, %sh_prom
+  %and1 = and i64 %shl, %bits
+  %tobool = icmp ne i64 %and1, 0
+  ret i1 %tobool
+}
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -15307,6 +15307,17 @@
   if (Src.getValueType() == MVT::i8 || Src.getValueType() == MVT::i16)
     Src = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Src);
 
+  // See if we can use the 32-bit instruction instead of the 64-bit one for a
+  // shorter encoding. Since the former takes the modulo 32 of BitNo and the
+  // latter takes the modulo 64, this is only valid if the 5th bit of BitNo is
+  // known to be zero.
+  if (Src.getValueType() == MVT::i64) {
+    APInt Zeros, Ones;
+    DAG.computeKnownBits(BitNo, Zeros, Ones);
+    if (Zeros[5])
+      Src = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src);
+  }
+
   // If the operand types disagree, extend the shift amount to match.  Since
   // BT ignores high bits (like shifts) we can use anyextend.
   if (Src.getValueType() != BitNo.getValueType())


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