[PATCH] D25580: [PowerPC] Improve handling of BUILD_VECTOR nodes (integer results)

[Eric Christopher via llvm-commits]

echristo added a comment.

Wow. This patch is huge. I don't know if some/any of it can be split up offhand.

Some inline comments.

-eric



================
Comment at: lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp:225
   const MCOperand &MO = MI.getOperand(OpNo);
-  if (MO.isImm())
+  // PPC::ZERO and PPC::ZERO8 are register MachineOperand's but they really
+  // represent immediates.
----------------
This seems... weird.


================
Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:7240
+          return false;
+        if (V->getOperand(i).getOpcode() == ISD::LOAD ||
+            (V->getOperand(i).getOpcode() == ISD::FP_ROUND &&
----------------
Might want to comment on the logic here.


================
Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:7277-7278
 
+  fprintf(stderr, "SplatBits = %u, SplatUndef = %u, SplatSize = %u\n",
+          SplatBits, SplatUndef, SplatSize);
   // We have XXSPLTIB for constant splats one byte wide
----------------
Debugging code - here and below.


================
Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:7282
+    fprintf(stderr, "Have P9 vector and SplatSize is 1\n");
+    // This is a splat other than some of the inputs are undef. Convert to
+    // a constant splat.
----------------
Not sure I understand this comment.


================
Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:10549
+SDValue
+PPCTargetLowering::combineBVOfFpToIntToFpToIntOfBV(SDNode *N,
+                                                   DAGCombinerInfo &DCI) const {
----------------
... this function name.


================
Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:10619
+
+static SDValue combineBVOfConsecutiveLoads(SDNode *N, SelectionDAG &DAG) {
+  assert(N->getOpcode() == ISD::BUILD_VECTOR &&
----------------
What's going on here?


================
Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:10734
   // Looking for:
   // (build_vector ([su]int_to_fp (extractelt 0)), [su]int_to_fp (extractelt 1))
+  if (FirstInput.getOpcode() != ISD::SINT_TO_FP &&
----------------
More comments like this.


Repository:
  rL LLVM

https://reviews.llvm.org/D25580