[PATCH] D25805: [AMDGPU] Perform uchar to float combine for ISD::SINT_TO_FP
Konstantin Zhuravlyov via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 19 17:03:32 PDT 2016
kzhuravl created this revision.
kzhuravl added a reviewer: tstellarAMD.
kzhuravl added a subscriber: llvm-commits.
Herald added subscribers: tony-tye, yaxunl, nhaehnle, wdng, arsenm.
https://reviews.llvm.org/D25805
Files:
lib/Target/AMDGPU/SIISelLowering.cpp
Index: lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- lib/Target/AMDGPU/SIISelLowering.cpp
+++ lib/Target/AMDGPU/SIISelLowering.cpp
@@ -233,6 +233,7 @@
setTargetDAGCombine(ISD::AND);
setTargetDAGCombine(ISD::OR);
setTargetDAGCombine(ISD::XOR);
+ setTargetDAGCombine(ISD::SINT_TO_FP);
setTargetDAGCombine(ISD::UINT_TO_FP);
setTargetDAGCombine(ISD::FCANONICALIZE);
@@ -3521,18 +3522,24 @@
case AMDGPUISD::CVT_F32_UBYTE3: {
unsigned Offset = N->getOpcode() - AMDGPUISD::CVT_F32_UBYTE0;
SDValue Src = N->getOperand(0);
+ if (Src.getOpcode() == ISD::ZERO_EXTEND &&
+ Src.getOperand(0).getOpcode() == ISD::SRL)
+ Src = Src.getOperand(0);
// TODO: Handle (or x, (srl y, 8)) pattern when known bits are zero.
if (Src.getOpcode() == ISD::SRL) {
// cvt_f32_ubyte0 (srl x, 16) -> cvt_f32_ubyte2 x
// cvt_f32_ubyte1 (srl x, 16) -> cvt_f32_ubyte3 x
// cvt_f32_ubyte0 (srl x, 8) -> cvt_f32_ubyte1 x
if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src.getOperand(1))) {
+ SDValue Chain = Src.getOperand(0).getScalarValueSizeInBits() < 32 ?
+ DAG.getNode(ISD::ZERO_EXTEND, SDLoc(Src.getOperand(0)),
+ EVT(MVT::i32), Src.getOperand(0)) : Src.getOperand(0);
unsigned SrcOffset = C->getZExtValue() + 8 * Offset;
if (SrcOffset < 32 && SrcOffset % 8 == 0) {
return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0 + SrcOffset / 8, DL,
- MVT::f32, Src.getOperand(0));
+ MVT::f32, Chain);
}
}
}
@@ -3550,7 +3557,7 @@
break;
}
-
+ case ISD::SINT_TO_FP:
case ISD::UINT_TO_FP: {
return performUCharToFloatCombine(N, DCI);
}
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