[llvm] r284607 - [DAGCombiner] Add general constant vector support to (shl (mul x, c1), c2) -> (mul x, c1 << c2)

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Wed Oct 19 10:59:28 2016
New Revision: 284607

URL: http://llvm.org/viewvc/llvm-project?rev=284607&view=rev
Log:
[DAGCombiner] Add general constant vector support to (shl (mul x, c1), c2) -> (mul x, c1 << c2)

We already supported scalar constant / splatted constant vector - now accepts any (non opaque) constant scalar / vector

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/X86/combine-shl.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=284607&r1=284606&r2=284607&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Oct 19 10:59:28 2016
@@ -4678,11 +4678,12 @@ SDValue DAGCombiner::visitSHL(SDNode *N)
   }
 
   // fold (shl (mul x, c1), c2) -> (mul x, c1 << c2)
-  if (N1C && N0.getOpcode() == ISD::MUL && N0.getNode()->hasOneUse()) {
-    if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
-      if (SDValue Folded =
-              DAG.FoldConstantArithmetic(ISD::SHL, SDLoc(N1), VT, N0C1, N1C))
-        return DAG.getNode(ISD::MUL, SDLoc(N), VT, N0.getOperand(0), Folded);
+  if (N0.getOpcode() == ISD::MUL && N0.getNode()->hasOneUse()) {
+    if (isConstantOrConstantVector(N1, /* No Opaques */ true) &&
+        isConstantOrConstantVector(N0.getOperand(1), /* No Opaques */ true)) {
+      SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N1), VT, N0.getOperand(1), N1);
+      AddToWorklist(Shl.getNode());
+      return DAG.getNode(ISD::MUL, SDLoc(N), VT, N0.getOperand(0), Shl);
     }
   }
 

Modified: llvm/trunk/test/CodeGen/X86/combine-shl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-shl.ll?rev=284607&r1=284606&r2=284607&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-shl.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-shl.ll Wed Oct 19 10:59:28 2016
@@ -572,7 +572,6 @@ define <4 x i32> @combine_vec_shl_mul1(<
 ; AVX-LABEL: combine_vec_shl_mul1:
 ; AVX:       # BB#0:
 ; AVX-NEXT:    vpmulld {{.*}}(%rip), %xmm0, %xmm0
-; AVX-NEXT:    vpsllvd {{.*}}(%rip), %xmm0, %xmm0
 ; AVX-NEXT:    retq
   %1 = mul <4 x i32> %x, <i32 5, i32 6, i32 7, i32 8>
   %2 = shl <4 x i32> %1, <i32 1, i32 2, i32 3, i32 4>