[llvm] r284460 - [ARM] Assign cost of scaling for Cortex-R52

[Javed Absar via llvm-commits]

Author: javed.absar
Date: Tue Oct 18 04:08:54 2016
New Revision: 284460

URL: http://llvm.org/viewvc/llvm-project?rev=284460&view=rev
Log:
[ARM] Assign cost of scaling for Cortex-R52

This patch assigns cost of the scaling used in addressing for Cortex-R52.

On Cortex-R52 a negated register offset takes longer than a non-negated
register offset, in a register-offset addressing mode.

Differential Revision: http://reviews.llvm.org/D25670

Reviewer: jmolloy


Modified:
    llvm/trunk/lib/Target/ARM/ARM.td
    llvm/trunk/test/CodeGen/ARM/lsr-scale-addr-mode.ll

Modified: llvm/trunk/lib/Target/ARM/ARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=284460&r1=284459&r2=284460&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.td (original)
+++ llvm/trunk/lib/Target/ARM/ARM.td Tue Oct 18 04:08:54 2016
@@ -823,7 +823,8 @@ def : ProcNoItin<"exynos-m2",
                                                          FeatureCrypto,
                                                          FeatureCRC]>;
 
-def : ProcNoItin<"cortex-r52",                          [ARMv8r, ProcR52]>;
+def : ProcNoItin<"cortex-r52",                          [ARMv8r, ProcR52,
+                                                         FeatureFPAO]>;
 
 //===----------------------------------------------------------------------===//
 // Register File Description

Modified: llvm/trunk/test/CodeGen/ARM/lsr-scale-addr-mode.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/lsr-scale-addr-mode.ll?rev=284460&r1=284459&r2=284460&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/lsr-scale-addr-mode.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/lsr-scale-addr-mode.ll Tue Oct 18 04:08:54 2016
@@ -1,8 +1,9 @@
 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
 ; Should use scaled addressing mode.
 
-; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a53 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF-A53
-; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a57 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF-A57
+; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a53 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF
+; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a57 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF
+; RUN: llc -mtriple=arm-eabi -mcpu=cortex-r52 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF
 ; Should not generate negated register offset
 
 define void @sintzero(i32* %a) nounwind {
@@ -23,6 +24,5 @@ return:		; preds = %cond_next
 }
 
 ; CHECK: lsl{{.*}}#2]
-; CHECK-NONEGOFF-A53: [{{r[0-9]+}}, {{r[0-9]+}}, lsl{{.*}}#2]
-; CHECK-NONEGOFF-A57: [{{r[0-9]+}}, {{r[0-9]+}}, lsl{{.*}}#2]
+; CHECK-NONEGOFF: [{{r[0-9]+}}, {{r[0-9]+}}, lsl{{.*}}#2]