[llvm] r284450 - [AVX-512] Add support for decoding shuffle mask from constant pool for masked VPERMILPS/PD.

[Davide Italiano via llvm-commits]

On Mon, Oct 17, 2016 at 8:36 PM, Craig Topper via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
> Author: ctopper
> Date: Mon Oct 17 22:36:52 2016
> New Revision: 284450
>
> URL: http://llvm.org/viewvc/llvm-project?rev=284450&view=rev
> Log:
> [AVX-512] Add support for decoding shuffle mask from constant pool for masked VPERMILPS/PD.
>

Can you add a testcase?

> Modified:
>     llvm/trunk/lib/Target/X86/X86MCInstLower.cpp
>
> Modified: llvm/trunk/lib/Target/X86/X86MCInstLower.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCInstLower.cpp?rev=284450&r1=284449&r2=284450&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86MCInstLower.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86MCInstLower.cpp Mon Oct 17 22:36:52 2016
> @@ -1527,44 +1527,73 @@ void X86AsmPrinter::EmitInstruction(cons
>      break;
>    }
>
> +  case X86::VPERMILPSrm:
> +  case X86::VPERMILPSYrm:
> +  case X86::VPERMILPSZ128rm:
> +  case X86::VPERMILPSZ128rmk:
> +  case X86::VPERMILPSZ128rmkz:
> +  case X86::VPERMILPSZ256rm:
> +  case X86::VPERMILPSZ256rmk:
> +  case X86::VPERMILPSZ256rmkz:
> +  case X86::VPERMILPSZrm:
> +  case X86::VPERMILPSZrmk:
> +  case X86::VPERMILPSZrmkz:
>    case X86::VPERMILPDrm:
>    case X86::VPERMILPDYrm:
>    case X86::VPERMILPDZ128rm:
> +  case X86::VPERMILPDZ128rmk:
> +  case X86::VPERMILPDZ128rmkz:
>    case X86::VPERMILPDZ256rm:
> -  case X86::VPERMILPDZrm: {
> +  case X86::VPERMILPDZ256rmk:
> +  case X86::VPERMILPDZ256rmkz:
> +  case X86::VPERMILPDZrm:
> +  case X86::VPERMILPDZrmk:
> +  case X86::VPERMILPDZrmkz: {
>      if (!OutStreamer->isVerboseAsm())
>        break;
> -    assert(MI->getNumOperands() >= 6 &&
> -           "We should always have at least 6 operands!");
> -    const MachineOperand &DstOp = MI->getOperand(0);
> -    const MachineOperand &SrcOp = MI->getOperand(1);
> -    const MachineOperand &MaskOp = MI->getOperand(5);
> -
> -    if (auto *C = getConstantFromPool(*MI, MaskOp)) {
> -      SmallVector<int, 8> Mask;
> -      DecodeVPERMILPMask(C, 64, Mask);
> -      if (!Mask.empty())
> -        OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, SrcOp, Mask));
> +    unsigned SrcIdx, MaskIdx;
> +    unsigned ElSize;
> +    switch (MI->getOpcode()) {
> +    default: llvm_unreachable("Invalid opcode");
> +    case X86::VPERMILPSrm:
> +    case X86::VPERMILPSYrm:
> +    case X86::VPERMILPSZ128rm:
> +    case X86::VPERMILPSZ256rm:
> +    case X86::VPERMILPSZrm:
> +      SrcIdx = 1; MaskIdx = 5; ElSize = 32; break;
> +    case X86::VPERMILPSZ128rmkz:
> +    case X86::VPERMILPSZ256rmkz:
> +    case X86::VPERMILPSZrmkz:
> +      SrcIdx = 2; MaskIdx = 6; ElSize = 32; break;
> +    case X86::VPERMILPSZ128rmk:
> +    case X86::VPERMILPSZ256rmk:
> +    case X86::VPERMILPSZrmk:
> +      SrcIdx = 3; MaskIdx = 7; ElSize = 32; break;
> +    case X86::VPERMILPDrm:
> +    case X86::VPERMILPDYrm:
> +    case X86::VPERMILPDZ128rm:
> +    case X86::VPERMILPDZ256rm:
> +    case X86::VPERMILPDZrm:
> +      SrcIdx = 1; MaskIdx = 5; ElSize = 64; break;
> +    case X86::VPERMILPDZ128rmkz:
> +    case X86::VPERMILPDZ256rmkz:
> +    case X86::VPERMILPDZrmkz:
> +      SrcIdx = 2; MaskIdx = 6; ElSize = 64; break;
> +    case X86::VPERMILPDZ128rmk:
> +    case X86::VPERMILPDZ256rmk:
> +    case X86::VPERMILPDZrmk:
> +      SrcIdx = 3; MaskIdx = 7; ElSize = 64; break;
>      }
> -    break;
> -  }
>
> -  case X86::VPERMILPSrm:
> -  case X86::VPERMILPSYrm:
> -  case X86::VPERMILPSZ128rm:
> -  case X86::VPERMILPSZ256rm:
> -  case X86::VPERMILPSZrm: {
> -    if (!OutStreamer->isVerboseAsm())
> -      break;
>      assert(MI->getNumOperands() >= 6 &&
>             "We should always have at least 6 operands!");
>      const MachineOperand &DstOp = MI->getOperand(0);
> -    const MachineOperand &SrcOp = MI->getOperand(1);
> -    const MachineOperand &MaskOp = MI->getOperand(5);
> +    const MachineOperand &SrcOp = MI->getOperand(SrcIdx);
> +    const MachineOperand &MaskOp = MI->getOperand(MaskIdx);
>
>      if (auto *C = getConstantFromPool(*MI, MaskOp)) {
>        SmallVector<int, 16> Mask;
> -      DecodeVPERMILPMask(C, 32, Mask);
> +      DecodeVPERMILPMask(C, ElSize, Mask);
>        if (!Mask.empty())
>          OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, SrcOp, Mask));
>      }
>
>
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-- 
Davide

"There are no solved problems; there are only problems that are more
or less solved" -- Henri Poincare